armtst.syr

Verilog编程

Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: armtst.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : armtst.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : armtst
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : armtst
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : armtst.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:Xst:878 - rom.v line 96: Unrecognized directive. Ignoring.
Compiling source file "my_dcm1.v"
Module <my_dcm1> compiled
Compiling source file "rom.v"
Module <rom> compiled
Compiling source file "armtst.v"
Module <armtst> compiled
No errors in compilation
Analysis of file <armtst.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:261 - armtst.v line 133 Connection to output port 'dout' does not match port size
Analyzing top module <armtst>.
Module <armtst> is correct for synthesis.
 
Analyzing module <my_dcm1>.
Module <my_dcm1> is correct for synthesis.
 
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKDV_DIVIDE =  2" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKFX_DIVIDE =  2" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKFX_MULTIPLY =  2" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKIN_PERIOD =  20" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <my_dcm1>.
Analyzing module <DCM>.
Analyzing module <IBUFG>.
Analyzing module <BUFG>.
Analyzing module <rom>.
WARNING:Xst:37 - Unknown property "fpga_dont_touch".

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <my_dcm1>.
    Related source file is my_dcm1.v.
Unit <my_dcm1> synthesized.


Synthesizing Unit <armtst>.
    Related source file is armtst.v.
    Found 16-bit 32-to-1 multiplexer for signal <$COND_1>.
    Found 16-bit register for signal <CONTROL>.
    Found 16-bit register for signal <fre_cont>.
    Found 512-bit register for signal <ram_data>.
    Found 16-bit up accumulator for signal <sum>.
    Found 16 1-bit 2-to-1 multiplexers.
INFO:Xst:738 - HDL ADVISOR - 512 flip-flops were inferred for signal <ram_data>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
    Summary:
	inferred   1 Accumulator(s).
	inferred 400 D-type flip-flop(s).
	inferred  32 Multiplexer(s).
Unit <armtst> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 34
  16-bit register                  : 34
# Accumulators                     : 1
  16-bit up accumulator            : 1
# Multiplexers                     : 2
  2-to-1 multiplexer               : 1
  16-bit 32-to-1 multiplexer       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "rom.ngo" is up to date.
Loading core <rom> for timing and area information for instance <sin>.

Optimizing unit <armtst> ...
Loading device for application Xst from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block armtst, actual ratio is 11.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : armtst.ngr
Top Level Output File Name         : armtst
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 50

Macro Statistics :
# Registers                        : 170
#      1-bit register              : 144
#      16-bit register             : 26
# Multiplexers                     : 2
#      16-bit 32-to-1 multiplexer  : 1
#      2-to-1 multiplexer          : 1