armtst.bld

来自「Verilog编程」· BLD 代码 · 共 81 行

BLD
81 行
字号 
Release 6.1.03i - ngdbuild G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -intstyle ise -dd e:\ise6.1\tst/_ngo -uc armtst_ucf.ucf
-p xc3s400-pq208-4 armtst.ngc armtst.ngd Reading NGO file "E:/ise6.1/tst/armtst.ngc" ...Reading component libraries for design expansion...Launcher: "rom.ngo" is up to date.Loading design module "e:\ise6.1\tst\_ngo\rom.ngo"...blkmemsp_v5_0, Coregen 6.1.03iAnnotating constraints to design from file "armtst_ucf.ucf" ...Attached a PULLDOWN primitive to pad net dout<0> Attached a PULLUP primitive to pad net NWE_n Attached a PULLUP primitive to pad net NCS3_n Attached a PULLDOWN primitive to pad net rst Attached a PULLDOWN primitive to pad net DataIN<15> Attached a PULLDOWN primitive to pad net DataIN<14> Attached a PULLDOWN primitive to pad net DataIN<13> Attached a PULLDOWN primitive to pad net DataIN<12> Attached a PULLDOWN primitive to pad net DataIN<11> Attached a PULLDOWN primitive to pad net DataIN<10> Attached a PULLDOWN primitive to pad net DataIN<9> Attached a PULLDOWN primitive to pad net DataIN<8> Attached a PULLDOWN primitive to pad net DataIN<7> Attached a PULLDOWN primitive to pad net DataIN<6> Attached a PULLDOWN primitive to pad net DataIN<5> Attached a PULLDOWN primitive to pad net DataIN<4> Attached a PULLDOWN primitive to pad net DataIN<3> Attached a PULLDOWN primitive to pad net DataIN<2> Attached a PULLDOWN primitive to pad net DataIN<1> Attached a PULLDOWN primitive to pad net DataIN<0> Attached a PULLDOWN primitive to pad net out<15> Attached a PULLDOWN primitive to pad net out<14> Attached a PULLDOWN primitive to pad net out<13> Attached a PULLDOWN primitive to pad net out<12> Attached a PULLDOWN primitive to pad net out<11> Attached a PULLDOWN primitive to pad net out<10> Attached a PULLDOWN primitive to pad net out<9> Attached a PULLDOWN primitive to pad net out<8> Attached a PULLDOWN primitive to pad net out<7> Attached a PULLDOWN primitive to pad net out<6> Attached a PULLDOWN primitive to pad net out<5> Attached a PULLDOWN primitive to pad net out<4> Attached a PULLDOWN primitive to pad net out<3> Attached a PULLDOWN primitive to pad net out<2> Attached a PULLDOWN primitive to pad net out<1> Attached a PULLDOWN primitive to pad net out<0> Attached a PULLDOWN primitive to pad net dout<7> Attached a PULLDOWN primitive to pad net dout<6> Attached a PULLDOWN primitive to pad net dout<5> Attached a PULLDOWN primitive to pad net dout<4> Attached a PULLDOWN primitive to pad net dout<3> Attached a PULLDOWN primitive to pad net dout<2> Attached a PULLDOWN primitive to pad net dout<1> Checking timing specifications ...Checking expanded design ...WARNING:NgdBuild:477 - clock net 'CLKDV_OUT' has non-clock connections. These
   problematic connections include:     pin I0 on block clk_out1 with type LUT1WARNING:NgdBuild:454 - logical net 'sin/dout<10>' has no loadWARNING:NgdBuild:454 - logical net 'sin/dout<11>' has no loadWARNING:NgdBuild:454 - logical net 'sin/dout<12>' has no loadWARNING:NgdBuild:454 - logical net 'sin/dout<13>' has no loadWARNING:NgdBuild:454 - logical net 'sin/dout<14>' has no loadWARNING:NgdBuild:454 - logical net 'sin/dout<15>' has no loadWARNING:NgdBuild:454 - logical net 'sin/dout<8>' has no loadWARNING:NgdBuild:454 - logical net 'sin/dout<9>' has no loadNGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   9Total memory usage is 43916 kilobytesWriting NGD file "armtst.ngd" ...Writing NGDBUILD log file "armtst.bld"...

armtst.bld - 源码说明

本页面展示了「Verilog编程」中的 armtst.bld 源码文件，采用 BLD 编程语言编写，共 81 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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