tst.v

Verilog编程

module tst(clk,
           A,
           DATA,
			  WE,
			  rst,
			  dout);

input clk;
input A;
input WE;
input rst;
input [27:0] DATA;
output [13:0] dout;

reg [27:0] sum;
wire [27:0] q;
wire [13:0] Q;
reg [27:0] POFF;
reg [27:0] PINC;

always @(posedge clk or posedge rst)

if(rst)
 begin
  POFF<=0;
  PINC<=0;
 end
else if(WE==1)
      begin
       if(A==0)
        PINC<=DATA;
       else
        POFF<=DATA;
		end
	  else
      begin
		 PINC<=PINC;
		 POFF<=POFF;			  
      end
   

always @(posedge clk or posedge rst)

if(rst)
  sum<=0;
else
  sum<=sum+PINC;

assign q=sum+POFF;
assign Q=q[27:14];

rom sin(
	         .addr(Q),
	         .clk(clk),
	         .dout(dout)
			   );
 
endmodule