top_tbw.fdo

Verilog编程

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu May 24 09:31:10 中国标准时间 2007
##
vlib work
vlog  my_dcm1.v
vlog  counter.v
vlog  rom1.v
vlog  DDS1.v
vlog  dds4.v
vlog  top.v
vlog  top_tbw.tfw
vlog  C:/Xilinx/verilog/src/glbl.v
vsim -t 1ps  -L xilinxcorelib_ver -L unisims_ver  -lib work top_tbw glbl
do top_tbw.udo
view wave
add wave *
view structure
view signals
run -all