tst1.par

Verilog编程

Constraints file: TST1.pcf

Loading device database for application Par from file "TST1_map.ncd".
   "TST1" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
C:/Xilinx.
Device speed data version:  PREVIEW 1.26 2003-06-19.


Resolved that IOB <clk> must be placed at site P79.
Resolved that IOB <out> must be placed at site P102.


Device utilization summary:

   Number of External IOBs             2 out of 141     1%
      Number of LOCed External IOBs    2 out of 2     100%





Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989681) REAL time: 2 secs 

Phase 3.8
Phase 3.8 (Checksum:989b11) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file TST1.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1 unrouted;       REAL time: 3 secs 

Phase 2: 1 unrouted;       REAL time: 3 secs 

Phase 3: 0 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 164


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.538
   The MAXIMUM PIN DELAY IS:                               1.538
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   0.513

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
           0           1           0           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  62 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file TST1.ncd.


PAR done.