tst.twr

Verilog编程

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Release 6.1i Trace G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml tst tst.ncd -o tst.twr
tst.pcf


Design file:              tst.ncd
Physical constraint file: tst.pcf
Device,speed:             xc3s400,-4 (PREVIEW 1.27 2003-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
A           |    4.514(R)|   -0.131(R)|clk_BUFGP         |   0.000|
DATA<0>     |    2.531(R)|    0.076(R)|clk_BUFGP         |   0.000|
DATA<10>    |    2.503(R)|    0.704(R)|clk_BUFGP         |   0.000|
DATA<11>    |    2.503(R)|    0.689(R)|clk_BUFGP         |   0.000|
DATA<12>    |    2.526(R)|    0.853(R)|clk_BUFGP         |   0.000|
DATA<13>    |    2.526(R)|   -0.064(R)|clk_BUFGP         |   0.000|
DATA<14>    |    2.520(R)|    0.859(R)|clk_BUFGP         |   0.000|
DATA<15>    |    2.520(R)|    0.719(R)|clk_BUFGP         |   0.000|
DATA<16>    |    2.530(R)|   -0.511(R)|clk_BUFGP         |   0.000|
DATA<17>    |    2.510(R)|    0.395(R)|clk_BUFGP         |   0.000|
DATA<18>    |    2.510(R)|    0.873(R)|clk_BUFGP         |   0.000|
DATA<19>    |    2.510(R)|    0.731(R)|clk_BUFGP         |   0.000|
DATA<1>     |    2.510(R)|    0.731(R)|clk_BUFGP         |   0.000|
DATA<20>    |    2.532(R)|    0.459(R)|clk_BUFGP         |   0.000|
DATA<21>    |    2.532(R)|    0.221(R)|clk_BUFGP         |   0.000|
DATA<22>    |    2.510(R)|    0.640(R)|clk_BUFGP         |   0.000|
DATA<23>    |    2.554(R)|   -0.075(R)|clk_BUFGP         |   0.000|
DATA<24>    |    2.526(R)|    0.355(R)|clk_BUFGP         |   0.000|
DATA<25>    |    2.527(R)|    0.528(R)|clk_BUFGP         |   0.000|
DATA<26>    |    2.527(R)|    0.453(R)|clk_BUFGP         |   0.000|
DATA<27>    |    2.532(R)|    0.379(R)|clk_BUFGP         |   0.000|
DATA<2>     |    2.526(R)|    0.657(R)|clk_BUFGP         |   0.000|
DATA<3>     |    2.521(R)|    0.719(R)|clk_BUFGP         |   0.000|
DATA<4>     |    2.515(R)|    0.865(R)|clk_BUFGP         |   0.000|
DATA<5>     |    2.526(R)|    0.348(R)|clk_BUFGP         |   0.000|
DATA<6>     |    2.515(R)|    0.608(R)|clk_BUFGP         |   0.000|
DATA<7>     |    2.510(R)|    0.643(R)|clk_BUFGP         |   0.000|
DATA<8>     |    2.521(R)|    0.162(R)|clk_BUFGP         |   0.000|
DATA<9>     |    2.503(R)|    0.738(R)|clk_BUFGP         |   0.000|
WE          |    5.373(R)|   -0.818(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dout<0>     |   12.868(R)|clk_BUFGP         |   0.000|
dout<1>     |   12.917(R)|clk_BUFGP         |   0.000|
dout<2>     |   12.710(R)|clk_BUFGP         |   0.000|
dout<3>     |   13.272(R)|clk_BUFGP         |   0.000|
dout<4>     |   12.916(R)|clk_BUFGP         |   0.000|
dout<5>     |   12.852(R)|clk_BUFGP         |   0.000|
dout<6>     |   12.440(R)|clk_BUFGP         |   0.000|
dout<7>     |   12.519(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    9.721|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sat Apr 28 11:06:50 2007
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Peak Memory Usage: 58 MB