dds_tbw.tfw

Verilog编程

// D:\商共享资料\程序\两路正弦波
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Tue Apr 22 16:57:52 2008
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

`define C_NOP	7
`define C_READ	5
`define IF2	3
`define s4	4
`define TCKO	0
`define s0	0
`define C_REFRSH	1
`define FCWIDTH	2
`define F_IDLE	1
`define F_DEASSERT	4
`define D	10
`define BR0	0
`define Q	25
`define s3	3
`define FDEPTH	4
`define C_ACTIVE	3
`define IF1	2
`define IF0	1
`define F_ASSERT	2
`define N	5
`define s1	1
`define C_L_MODE	0
`define OD	4
`define C_WRITE	4
`define C_P_CHRG	2
`define s2	2
`define state_delay	6
`define FWIDTH	32
`define TCKO	0
`define C_READ	5
`define C_REFRSH	1
`define RES	5
`define C_WRITE	4
`define F_ASSERT	2
`define IF1	2

module dds_tbw;
	reg [15:0] DATA_FRE;
	reg [15:0] DATA_PHA;
	reg [15:0] PHA_ACC;
	reg WE;
	reg CLK;
	reg SCLR;
	reg rst;
	wire [10:0] SINE;

	DDS1 UUT (
		.DATA_FRE(DATA_FRE),
		.DATA_PHA(DATA_PHA),
		.PHA_ACC(PHA_ACC),
		.WE(WE),
		.CLK(CLK),
		.SCLR(SCLR),
		.rst(rst),
		.SINE(SINE)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	CLK = 1'b0;
	#5
	CLK = 1'b1;
	#5
	#5
	CLK = 1'b0;
	#5
	CLK = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("results.txt");

	// --------------------
	DATA_FRE = 16'b0000000000000000; //0
	DATA_PHA = 16'b0000000000000000; //0
	PHA_ACC = 16'b0000000000000000; //0
	WE = 1'b0;
	SCLR = 1'b0;
	rst = 1'b0;
	// --------------------
	#20 // Time=20 ns
	// --------------------

	if (TX_ERROR == 0) begin
		$display("No errors or warnings");
		$fdisplay(TX_FILE,"No errors or warnings");
	end else begin
		$display("%d errors found in simulation",TX_ERROR);
		$fdisplay(TX_FILE,"%d errors found in simulation",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task CHECK_SINE;
	input [10:0] NEXT_SINE;

	#0 begin
		if (NEXT_SINE !== SINE) begin
			$display("Error at time=%dns SINE=%b, expected=%b",
				$time, SINE, NEXT_SINE);
			$fdisplay(TX_FILE,"Error at time=%dns SINE=%b, expected=%b",
				$time, SINE, NEXT_SINE);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

endmodule