dds1.par

Verilog编程

Constraints file: DDS1.pcf

Loading device database for application Par from file "DDS1_map.ncd".
   "DDS1" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/Xilinx.
Device speed data version:  PREVIEW 1.26 2003-06-19.


Device utilization summary:

   Number of External IOBs            47 out of 141    33%
      Number of LOCed External IOBs    0 out of 47      0%

   Number of MULT18X18s                1 out of 16      6%
   Number of RAMB16s                   1 out of 16      6%
   Number of SLICELs                  19 out of 3584    1%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897c9) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.
Phase 5.8 (Checksum:99f240) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file DDS1.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 273 unrouted;       REAL time: 2 secs 

Phase 2: 210 unrouted;       REAL time: 3 secs 

Phase 3: 33 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         CLK_BUFGP       |  BUFGMUX0| No   |   48 |  0.161     |  0.508      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 177


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.135
   The MAXIMUM PIN DELAY IS:                               4.032
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.151

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         138          99          25          10           1           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  67 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file DDS1.ncd.


PAR done.