tst.bld

Verilog编程

Release 6.1.03i - ngdbuild G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -intstyle ise -dd e:\ise6.1\tst/_ngo -i -p
xc3s400-pq208-4 tst.ngc tst.ngd 

Reading NGO file "E:/ise6.1/tst/tst.ngc" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa "rom.edn" "e:\ise6.1\tst\_ngo\rom.ngo"
INFO:NgdBuild - Release 6.1.03i - edif2ngd G.26
INFO:NgdBuild - Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Writing the design to "e:/ise6.1/tst/_ngo/rom.ngo"...
Loading design module "e:\ise6.1\tst\_ngo\rom.ngo"...
blkmemsp_v5_0, Coregen 6.1.03i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'sin/dout<10>' has no load
WARNING:NgdBuild:454 - logical net 'sin/dout<11>' has no load
WARNING:NgdBuild:454 - logical net 'sin/dout<12>' has no load
WARNING:NgdBuild:454 - logical net 'sin/dout<13>' has no load
WARNING:NgdBuild:454 - logical net 'sin/dout<14>' has no load
WARNING:NgdBuild:454 - logical net 'sin/dout<15>' has no load
WARNING:NgdBuild:454 - logical net 'sin/dout<8>' has no load
WARNING:NgdBuild:454 - logical net 'sin/dout<9>' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   8

Total memory usage is 39880 kilobytes

Writing NGD file "tst.ngd" ...

Writing NGDBUILD log file "tst.bld"...