a1.twr

来自「Verilog编程」· TWR 代码 · 共 35 行

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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml a1 a1.ncd -o a1.twr
a1.pcf


Design file:              a1.ncd
Physical constraint file: a1.pcf
Device,speed:             xc3s400,-4 (PREVIEW 1.26 2003-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.

Analysis completed Mon May 21 22:45:41 2007
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Peak Memory Usage: 55 MB