dds1.twr

来自「Verilog编程」· TWR 代码 · 共 100 行

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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml DDS1 DDS1.ncd -o
DDS1.twr DDS1.pcf


Design file:              DDS1.ncd
Physical constraint file: DDS1.pcf
Device,speed:             xc3s400,-4 (PREVIEW 1.26 2003-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
DATA_FRE<0> |    3.182(R)|   -1.131(R)|CLK_BUFGP         |   0.000|
DATA_FRE<10>|    3.177(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_FRE<11>|    3.177(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_FRE<12>|    3.176(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_FRE<13>|    3.240(R)|   -1.199(R)|CLK_BUFGP         |   0.000|
DATA_FRE<14>|    3.199(R)|   -1.151(R)|CLK_BUFGP         |   0.000|
DATA_FRE<15>|    3.176(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_FRE<1> |    3.182(R)|   -1.131(R)|CLK_BUFGP         |   0.000|
DATA_FRE<2> |    3.108(R)|   -1.044(R)|CLK_BUFGP         |   0.000|
DATA_FRE<3> |    3.170(R)|   -1.117(R)|CLK_BUFGP         |   0.000|
DATA_FRE<4> |    3.170(R)|   -1.117(R)|CLK_BUFGP         |   0.000|
DATA_FRE<5> |    3.170(R)|   -1.117(R)|CLK_BUFGP         |   0.000|
DATA_FRE<6> |    3.170(R)|   -1.117(R)|CLK_BUFGP         |   0.000|
DATA_FRE<7> |    3.170(R)|   -1.117(R)|CLK_BUFGP         |   0.000|
DATA_FRE<8> |    3.170(R)|   -1.117(R)|CLK_BUFGP         |   0.000|
DATA_FRE<9> |    3.176(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_PHA<0> |    3.176(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_PHA<10>|    3.245(R)|   -1.205(R)|CLK_BUFGP         |   0.000|
DATA_PHA<11>|    3.175(R)|   -1.122(R)|CLK_BUFGP         |   0.000|
DATA_PHA<12>|    3.240(R)|   -1.199(R)|CLK_BUFGP         |   0.000|
DATA_PHA<13>|    3.208(R)|   -1.162(R)|CLK_BUFGP         |   0.000|
DATA_PHA<14>|    3.199(R)|   -1.151(R)|CLK_BUFGP         |   0.000|
DATA_PHA<15>|    3.182(R)|   -1.131(R)|CLK_BUFGP         |   0.000|
DATA_PHA<1> |    3.182(R)|   -1.130(R)|CLK_BUFGP         |   0.000|
DATA_PHA<2> |    3.171(R)|   -1.117(R)|CLK_BUFGP         |   0.000|
DATA_PHA<3> |    3.171(R)|   -1.117(R)|CLK_BUFGP         |   0.000|
DATA_PHA<4> |    3.176(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_PHA<5> |    3.171(R)|   -1.117(R)|CLK_BUFGP         |   0.000|
DATA_PHA<6> |    3.176(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_PHA<7> |    3.176(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_PHA<8> |    3.176(R)|   -1.124(R)|CLK_BUFGP         |   0.000|
DATA_PHA<9> |    3.181(R)|   -1.130(R)|CLK_BUFGP         |   0.000|
SCLR        |    1.606(R)|    0.064(R)|CLK_BUFGP         |   0.000|
WE          |    3.346(R)|    1.407(R)|CLK_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
SINE<0>     |   15.490(R)|CLK_BUFGP         |   0.000|
SINE<10>    |   17.148(R)|CLK_BUFGP         |   0.000|
SINE<1>     |   15.923(R)|CLK_BUFGP         |   0.000|
SINE<2>     |   16.254(R)|CLK_BUFGP         |   0.000|
SINE<3>     |   16.420(R)|CLK_BUFGP         |   0.000|
SINE<4>     |   15.797(R)|CLK_BUFGP         |   0.000|
SINE<5>     |   16.284(R)|CLK_BUFGP         |   0.000|
SINE<6>     |   16.720(R)|CLK_BUFGP         |   0.000|
SINE<7>     |   16.283(R)|CLK_BUFGP         |   0.000|
SINE<8>     |   17.034(R)|CLK_BUFGP         |   0.000|
SINE<9>     |   16.685(R)|CLK_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    6.895|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Aug 16 15:37:12 2007
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Peak Memory Usage: 58 MB