counter_tbw.ant

Verilog编程

// E:\ISE6.1\TST
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Thu Apr 26 20:53:30 2007

`timescale 1ns/1ns

`define s3	3
`define s2	2
`define C_READ	5
`define C_WRITE	4
`define C_P_CHRG	2
`define C_ACTIVE	3
`define C_L_MODE	0
`define s1	1
`define F_ASSERT	2
`define state_delay	6
`define FWIDTH	32
`define OD	4
`define IF1	2
`define D	10
`define F_IDLE	1
`define C_NOP	7
`define s0	0
`define FCWIDTH	2
`define Q	25
`define RES	5
`define TCKO	0
`define s4	4
`define IF2	3
`define IF0	1
`define N	5
`define C_REFRSH	1
`define BR0	0
`define F_DEASSERT	4
`define FDEPTH	4

module counter_tbw;
	reg rst;
	reg inclk;
	wire outclk;
	reg [25:0] clkdata;

	counter UUT (
		.rst(rst),
		.inclk(inclk),
		.outclk(outclk),
		.clkdata(clkdata)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	inclk = 1'b0;
	#5
	inclk = 1'b1;
	#5
	ANNOTATE_outclk;
	#5
	inclk = 1'b0;
	#5
	inclk = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("e:\\ise6.1\\tst\\counter_tbw.ano");

	// --------------------
	rst = 1'b0;
	clkdata = 26'b00000000000000000000000000; //0
	// --------------------
	#20 // Time=20 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_outclk;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,outclk,%b]",
			$time, outclk);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule