dds4.v

Verilog编程

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:26:15 03/26/2007 
// Design Name: 
// Module Name:    dds4 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module dds4(DATA_FRE1,
            DATA_FRE2,
				DATA_FRE3,
				DATA_FRE4,
				DATA_FRE5,
				DATA_FRE6,
				
				DATA_PHA1,
				DATA_PHA2,
				DATA_PHA3,
				DATA_PHA4,
				DATA_PHA5,
				DATA_PHA6,
				
				PHA_ACC1,
				PHA_ACC2,
				PHA_ACC3,
				PHA_ACC4,
				PHA_ACC5,
				PHA_ACC6,
							
				CONTROL,
			//	BUTTON,
				RST,
			
				CLK0,
				
				SINE1,
				SINE2,
				SINE3,
				SINE4,
				SINE5,
				SINE6
    );

input [15:0] DATA_FRE1,DATA_PHA1,PHA_ACC1;
input [15:0] DATA_FRE2,DATA_PHA2,PHA_ACC2;
input [15:0] DATA_FRE3,DATA_PHA3,PHA_ACC3;
input [15:0] DATA_FRE4,DATA_PHA4,PHA_ACC4;
input [15:0] DATA_FRE5,DATA_PHA5,PHA_ACC5;
input [15:0] DATA_FRE6,DATA_PHA6,PHA_ACC6;

input [15:0] CONTROL;
//input BUTTON;
input RST;

input CLK0;

output [10:0] SINE1;
output [10:0] SINE2;
output [10:0] SINE3;
output [10:0] SINE4; 
output [10:0] SINE5;
output [10:0] SINE6; 



reg  SCLR1,SCLR2,SCLR3,SCLR4,SCLR5,SCLR6;			  //高电平有效，reg清零
reg  WE1,WE2,WE3,WE4,WE5,WE6;						 //高电平允许写入信号


always @(posedge CLK0 or posedge RST)

if(RST)
begin
SCLR1<=1;
SCLR2<=1;
SCLR3<=1;
SCLR4<=1;
SCLR5<=1;
SCLR6<=1;
WE1<=0;
WE2<=0;
WE3<=0;
WE4<=0;
WE5<=0;
WE6<=0;
end
else
begin
SCLR1<=CONTROL[15];
SCLR2<=CONTROL[14];
SCLR3<=CONTROL[13];
SCLR4<=CONTROL[12];
SCLR5<=CONTROL[11];
SCLR6<=CONTROL[10];
WE1<=CONTROL[9];
WE2<=CONTROL[8];
WE3<=CONTROL[7];
WE4<=CONTROL[6];
WE5<=CONTROL[5];
WE6<=CONTROL[4];

end


DDS1 DDS10(
    .DATA_FRE(DATA_FRE1), 
    .DATA_PHA(DATA_PHA1),
    .PHA_ACC(PHA_ACC1),	 
    .WE(WE1), 
    .CLK(CLK0), 
    .SCLR(SCLR1), 
    .rst(RST), 
    .SINE(SINE1)
    );

DDS1 DDS20(
    .DATA_FRE(DATA_FRE2), 
    .DATA_PHA(DATA_PHA2),
    .PHA_ACC(PHA_ACC2),	 
    .WE(WE2), 
    .CLK(CLK0), 
    .SCLR(SCLR2), 
    .rst(RST), 
    .SINE(SINE2)
    );

DDS1 DDS30(
    .DATA_FRE(DATA_FRE3), 
    .DATA_PHA(DATA_PHA3),
    .PHA_ACC(PHA_ACC3),	 
    .WE(WE3), 
    .CLK(CLK0), 
    .SCLR(SCLR3), 
    .rst(RST), 
    .SINE(SINE3)
    );

DDS1 DDS40(
    .DATA_FRE(DATA_FRE4), 
    .DATA_PHA(DATA_PHA4), 
	 .PHA_ACC(PHA_ACC4),
    .WE(WE4), 
    .CLK(CLK0), 
    .SCLR(SCLR4), 
    .rst(RST), 
    .SINE(SINE4)
    );

	 
DDS1 DDS50(
    .DATA_FRE(DATA_FRE5), 
    .DATA_PHA(DATA_PHA5),
    .PHA_ACC(PHA_ACC5),	 
    .WE(WE5), 
    .CLK(CLK0), 
    .SCLR(SCLR5), 
    .rst(RST), 
    .SINE(SINE5)
    );
	 
DDS1 DDS60(
    .DATA_FRE(DATA_FRE6), 
    .DATA_PHA(DATA_PHA6), 
	 .PHA_ACC(PHA_ACC6),
    .WE(WE6), 
    .CLK(CLK0), 
    .SCLR(SCLR6), 
    .rst(RST), 
    .SINE(SINE6)
    );
 
//assign SINE1=SINE_T1+8'b10000000;
//assign SINE2=SINE_T2+8'b10000000;
//assign SINE3=SINE_T3+8'b10000000;
//assign SINE4=SINE_T4+8'b10000000;


endmodule