armtst_translate.v

Verilog编程

  wire \ram_data_19_8.GSR.OR ;
  wire \ram_data_19_9.GSR.OR ;
  wire \ram_data_19_10.GSR.OR ;
  wire \ram_data_19_11.GSR.OR ;
  wire \ram_data_19_12.GSR.OR ;
  wire \ram_data_19_13.GSR.OR ;
  wire \ram_data_19_14.GSR.OR ;
  wire \ram_data_18_0.GSR.OR ;
  wire \ram_data_18_1.GSR.OR ;
  wire \ram_data_18_2.GSR.OR ;
  wire \ram_data_18_3.GSR.OR ;
  wire \ram_data_18_4.GSR.OR ;
  wire \ram_data_18_5.GSR.OR ;
  wire \ram_data_18_6.GSR.OR ;
  wire \ram_data_18_7.GSR.OR ;
  wire \ram_data_18_8.GSR.OR ;
  wire \ram_data_18_9.GSR.OR ;
  wire \ram_data_18_10.GSR.OR ;
  wire \ram_data_18_11.GSR.OR ;
  wire \ram_data_18_12.GSR.OR ;
  wire \ram_data_18_13.GSR.OR ;
  wire \ram_data_18_14.GSR.OR ;
  wire \ram_data_17_0.GSR.OR ;
  wire \ram_data_17_1.GSR.OR ;
  wire \ram_data_17_2.GSR.OR ;
  wire \ram_data_17_3.GSR.OR ;
  wire \ram_data_17_4.GSR.OR ;
  wire \ram_data_17_5.GSR.OR ;
  wire \ram_data_17_6.GSR.OR ;
  wire \ram_data_17_7.GSR.OR ;
  wire \ram_data_17_8.GSR.OR ;
  wire \ram_data_17_9.GSR.OR ;
  wire \ram_data_17_10.GSR.OR ;
  wire \ram_data_17_11.GSR.OR ;
  wire \ram_data_17_12.GSR.OR ;
  wire \ram_data_17_13.GSR.OR ;
  wire \ram_data_17_14.GSR.OR ;
  wire \ram_data_16_0.GSR.OR ;
  wire \ram_data_16_1.GSR.OR ;
  wire \ram_data_16_2.GSR.OR ;
  wire \ram_data_16_3.GSR.OR ;
  wire \ram_data_16_4.GSR.OR ;
  wire \ram_data_16_5.GSR.OR ;
  wire \ram_data_16_6.GSR.OR ;
  wire \ram_data_16_7.GSR.OR ;
  wire \ram_data_16_8.GSR.OR ;
  wire \ram_data_16_9.GSR.OR ;
  wire \ram_data_16_10.GSR.OR ;
  wire \ram_data_16_11.GSR.OR ;
  wire \ram_data_16_12.GSR.OR ;
  wire \ram_data_16_13.GSR.OR ;
  wire \ram_data_16_14.GSR.OR ;
  wire \ram_data_15_0.GSR.OR ;
  wire \ram_data_15_1.GSR.OR ;
  wire \ram_data_15_2.GSR.OR ;
  wire \ram_data_15_3.GSR.OR ;
  wire \ram_data_15_4.GSR.OR ;
  wire \ram_data_15_5.GSR.OR ;
  wire \ram_data_15_6.GSR.OR ;
  wire \ram_data_15_7.GSR.OR ;
  wire \ram_data_15_8.GSR.OR ;
  wire \sum_15.GSR.OR ;
  wire \sum_0.GSR.OR ;
  wire \sum_1.GSR.OR ;
  wire \sum_2.GSR.OR ;
  wire \sum_3.GSR.OR ;
  wire \sum_4.GSR.OR ;
  wire \sum_5.GSR.OR ;
  wire \sum_6.GSR.OR ;
  wire \sum_7.GSR.OR ;
  wire \sum_8.GSR.OR ;
  wire \sum_9.GSR.OR ;
  wire \sum_10.GSR.OR ;
  wire \sum_11.GSR.OR ;
  wire \sum_12.GSR.OR ;
  wire \sum_13.GSR.OR ;
  wire \ram_data_13_15.GSR.OR ;
  wire \ram_data_13_14.GSR.OR ;
  wire \ram_data_13_0.GSR.OR ;
  wire \ram_data_13_1.GSR.OR ;
  wire \ram_data_13_2.GSR.OR ;
  wire \ram_data_13_3.GSR.OR ;
  wire \ram_data_13_4.GSR.OR ;
  wire \ram_data_13_5.GSR.OR ;
  wire \ram_data_13_6.GSR.OR ;
  wire \ram_data_13_7.GSR.OR ;
  wire \ram_data_13_8.GSR.OR ;
  wire \ram_data_13_9.GSR.OR ;
  wire \ram_data_13_10.GSR.OR ;
  wire \ram_data_13_11.GSR.OR ;
  wire \ram_data_13_12.GSR.OR ;
  wire \ram_data_11_15.GSR.OR ;
  wire \ram_data_11_14.GSR.OR ;
  wire \ram_data_11_0.GSR.OR ;
  wire \ram_data_11_1.GSR.OR ;
  wire \ram_data_11_2.GSR.OR ;
  wire \ram_data_11_3.GSR.OR ;
  wire \ram_data_11_4.GSR.OR ;
  wire \ram_data_11_5.GSR.OR ;
  wire \ram_data_11_6.GSR.OR ;
  wire \ram_data_11_7.GSR.OR ;
  wire \ram_data_11_8.GSR.OR ;
  wire \ram_data_11_9.GSR.OR ;
  wire \ram_data_11_10.GSR.OR ;
  wire \ram_data_11_11.GSR.OR ;
  wire \ram_data_11_12.GSR.OR ;
  wire \ram_data_6_15.GSR.OR ;
  wire \ram_data_6_14.GSR.OR ;
  wire \ram_data_6_0.GSR.OR ;
  wire \ram_data_6_1.GSR.OR ;
  wire \ram_data_6_2.GSR.OR ;
  wire \ram_data_6_3.GSR.OR ;
  wire \ram_data_6_4.GSR.OR ;
  wire \ram_data_6_5.GSR.OR ;
  wire \ram_data_6_6.GSR.OR ;
  wire \ram_data_6_7.GSR.OR ;
  wire \ram_data_6_8.GSR.OR ;
  wire \ram_data_6_9.GSR.OR ;
  wire \ram_data_6_10.GSR.OR ;
  wire \ram_data_6_11.GSR.OR ;
  wire \ram_data_6_12.GSR.OR ;
  wire \ram_data_5_15.GSR.OR ;
  wire \ram_data_5_14.GSR.OR ;
  wire \ram_data_5_0.GSR.OR ;
  wire \ram_data_5_1.GSR.OR ;
  wire \ram_data_5_2.GSR.OR ;
  wire \ram_data_5_3.GSR.OR ;
  wire \ram_data_5_4.GSR.OR ;
  wire \ram_data_5_5.GSR.OR ;
  wire \ram_data_5_6.GSR.OR ;
  wire \ram_data_5_7.GSR.OR ;
  wire \ram_data_5_8.GSR.OR ;
  wire \ram_data_5_9.GSR.OR ;
  wire \ram_data_5_10.GSR.OR ;
  wire \ram_data_5_11.GSR.OR ;
  wire \ram_data_5_12.GSR.OR ;
  wire \ram_data_4_15.GSR.OR ;
  wire \ram_data_4_14.GSR.OR ;
  wire \ram_data_4_0.GSR.OR ;
  wire \ram_data_4_1.GSR.OR ;
  wire \ram_data_4_2.GSR.OR ;
  wire \ram_data_4_3.GSR.OR ;
  wire \ram_data_4_4.GSR.OR ;
  wire \ram_data_4_5.GSR.OR ;
  wire \ram_data_4_6.GSR.OR ;
  wire \ram_data_4_7.GSR.OR ;
  wire \ram_data_4_8.GSR.OR ;
  wire \ram_data_4_9.GSR.OR ;
  wire \ram_data_4_10.GSR.OR ;
  wire \ram_data_4_11.GSR.OR ;
  wire \ram_data_4_12.GSR.OR ;
  wire \ram_data_3_15.GSR.OR ;
  wire \ram_data_3_14.GSR.OR ;
  wire \ram_data_3_0.GSR.OR ;
  wire \ram_data_3_1.GSR.OR ;
  wire \ram_data_3_2.GSR.OR ;
  wire \ram_data_3_3.GSR.OR ;
  wire \ram_data_3_4.GSR.OR ;
  wire \ram_data_3_5.GSR.OR ;
  wire \ram_data_3_6.GSR.OR ;
  wire \ram_data_3_7.GSR.OR ;
  wire \ram_data_3_8.GSR.OR ;
  wire \ram_data_3_9.GSR.OR ;
  wire \ram_data_3_10.GSR.OR ;
  wire \ram_data_3_11.GSR.OR ;
  wire \ram_data_3_12.GSR.OR ;
  wire \ram_data_2_15.GSR.OR ;
  wire \ram_data_2_14.GSR.OR ;
  wire \ram_data_2_0.GSR.OR ;
  wire \ram_data_2_1.GSR.OR ;
  wire \ram_data_2_2.GSR.OR ;
  wire \ram_data_2_3.GSR.OR ;
  wire \ram_data_2_4.GSR.OR ;
  wire \ram_data_2_5.GSR.OR ;
  wire \ram_data_2_6.GSR.OR ;
  wire \ram_data_2_7.GSR.OR ;
  wire \ram_data_2_8.GSR.OR ;
  wire \ram_data_2_9.GSR.OR ;
  wire \ram_data_2_10.GSR.OR ;
  wire \ram_data_2_11.GSR.OR ;
  wire \ram_data_2_12.GSR.OR ;
  wire \ram_data_1_15.GSR.OR ;
  wire \ram_data_1_14.GSR.OR ;
  wire \ram_data_1_0.GSR.OR ;
  wire \ram_data_1_1.GSR.OR ;
  wire \ram_data_1_2.GSR.OR ;
  wire \ram_data_1_3.GSR.OR ;
  wire \ram_data_1_4.GSR.OR ;
  wire \ram_data_1_5.GSR.OR ;
  wire \ram_data_1_6.GSR.OR ;
  wire \ram_data_1_7.GSR.OR ;
  wire \ram_data_1_8.GSR.OR ;
  wire \ram_data_1_9.GSR.OR ;
  wire \ram_data_1_10.GSR.OR ;
  wire \ram_data_1_11.GSR.OR ;
  wire \ram_data_1_12.GSR.OR ;
  wire \ram_data_0_15.GSR.OR ;
  wire \ram_data_0_14.GSR.OR ;
  wire \ram_data_0_0.GSR.OR ;
  wire \ram_data_0_1.GSR.OR ;
  wire \ram_data_0_2.GSR.OR ;
  wire \ram_data_0_3.GSR.OR ;
  wire \ram_data_0_4.GSR.OR ;
  wire \ram_data_0_5.GSR.OR ;
  wire \ram_data_0_6.GSR.OR ;
  wire \ram_data_0_7.GSR.OR ;
  wire \ram_data_0_8.GSR.OR ;
  wire \ram_data_0_9.GSR.OR ;
  wire \ram_data_0_10.GSR.OR ;
  wire \ram_data_0_11.GSR.OR ;
  wire \ram_data_0_12.GSR.OR ;
  wire \dout_0_OBUF.GTS.TRI ;
  wire GTS = glbl.GTS;
  wire \clk_out_OBUF.GTS.TRI ;
  wire \out_15_OBUF.GTS.TRI ;
  wire \out_14_OBUF.GTS.TRI ;
  wire \out_13_OBUF.GTS.TRI ;
  wire \out_12_OBUF.GTS.TRI ;
  wire \out_11_OBUF.GTS.TRI ;
  wire \out_10_OBUF.GTS.TRI ;
  wire \out_9_OBUF.GTS.TRI ;
  wire \out_8_OBUF.GTS.TRI ;
  wire \out_7_OBUF.GTS.TRI ;
  wire \out_6_OBUF.GTS.TRI ;
  wire \out_5_OBUF.GTS.TRI ;
  wire \out_4_OBUF.GTS.TRI ;
  wire \out_3_OBUF.GTS.TRI ;
  wire \out_2_OBUF.GTS.TRI ;
  wire \out_1_OBUF.GTS.TRI ;
  wire \out_0_OBUF.GTS.TRI ;
  wire \dout_7_OBUF.GTS.TRI ;
  wire \dout_6_OBUF.GTS.TRI ;
  wire \dout_5_OBUF.GTS.TRI ;
  wire \dout_4_OBUF.GTS.TRI ;
  wire \dout_3_OBUF.GTS.TRI ;
  wire \dout_2_OBUF.GTS.TRI ;
  wire \dout_1_OBUF.GTS.TRI ;
  wire GND;
  wire VCC;
  wire NLW_instance_name_CLK180_BUFG_INST_O_UNCONNECTED;
  wire NLW_instance_name_DCM_INST_CLK90_UNCONNECTED;
  wire NLW_instance_name_DCM_INST_CLK270_UNCONNECTED;
  wire NLW_instance_name_DCM_INST_CLK2X_UNCONNECTED;
  wire NLW_instance_name_DCM_INST_CLK2X180_UNCONNECTED;
  wire NLW_instance_name_DCM_INST_CLKDV_UNCONNECTED;
  wire NLW_instance_name_DCM_INST_CLKFX180_UNCONNECTED;
  wire NLW_instance_name_DCM_INST_LOCKED_UNCONNECTED;
  wire NLW_instance_name_DCM_INST_PSDONE_UNCONNECTED;
  wire \NLW_instance_name_DCM_INST_STATUS[7]_UNCONNECTED ;
  wire \NLW_instance_name_DCM_INST_STATUS[6]_UNCONNECTED ;
  wire \NLW_instance_name_DCM_INST_STATUS[5]_UNCONNECTED ;
  wire \NLW_instance_name_DCM_INST_STATUS[4]_UNCONNECTED ;
  wire \NLW_instance_name_DCM_INST_STATUS[3]_UNCONNECTED ;
  wire \NLW_instance_name_DCM_INST_STATUS[2]_UNCONNECTED ;
  wire \NLW_instance_name_DCM_INST_STATUS[1]_UNCONNECTED ;
  wire \NLW_instance_name_DCM_INST_STATUS[0]_UNCONNECTED ;
  wire \NLW_sin/B5_DOP[0]_UNCONNECTED ;
  wire \NLW_sin/B5_DOP[1]_UNCONNECTED ;
  wire \NlwInverterSignal_dout_0_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_clk_out_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_15_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_14_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_13_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_12_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_11_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_10_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_9_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_8_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_7_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_6_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_5_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_4_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_3_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_2_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_1_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_out_0_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_dout_7_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_dout_6_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_dout_5_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_dout_4_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_dout_3_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_dout_2_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_dout_1_OBUF.GTS.TRI/CTL ;
  wire [15 : 0] CONTROL;
  wire [15 : 0] fre_cont;
  wire [15 : 0] _n0263;
  wire [15 : 0] _n0032;
  wire [15 : 0] sum;
  wire [15 : 1] sum__n0000;
  wire [7 : 0] NlwRenamedSig_OI_dout;
  wire [15 : 0] NlwRenamedSig_IO_DataIN;
  wire [15 : 0] NlwRenamedSig_OI_out;
  wire [15 : 8] \sin/dout ;
  assign
    NlwRenamedSig_IO_NCS3_n = NCS3_n,
    NlwRenamedSig_IO_rst = rst,
    NlwRenamedSig_IO_NWE_n = NWE_n,
    NlwRenamedSig_IO_DataIN[15] = DataIN[15],
    NlwRenamedSig_IO_DataIN[14] = DataIN[14],
    NlwRenamedSig_IO_DataIN[13] = DataIN[13],
    NlwRenamedSig_IO_DataIN[12] = DataIN[12],
    NlwRenamedSig_IO_DataIN[11] = DataIN[11],
    NlwRenamedSig_IO_DataIN[10] = DataIN[10],
    NlwRenamedSig_IO_DataIN[9] = DataIN[9],
    NlwRenamedSig_IO_DataIN[8] = DataIN[8],
    NlwRenamedSig_IO_DataIN[7] = DataIN[7],
    NlwRenamedSig_IO_DataIN[6] = DataIN[6],
    NlwRenamedSig_IO_DataIN[5] = DataIN[5],
    NlwRenamedSig_IO_DataIN[4] = DataIN[4],
    NlwRenamedSig_IO_DataIN[3] = DataIN[3],
    NlwRenamedSig_IO_DataIN[2] = DataIN[2],
    NlwRenamedSig_IO_DataIN[1] = DataIN[1],
    NlwRenamedSig_IO_DataIN[0] = DataIN[0],
    out[15] = NlwRenamedSig_OI_out[15],
    out[14] = NlwRenamedSig_OI_out[14],
    out[13] = NlwRenamedSig_OI_out[13],
    out[12] = NlwRenamedSig_OI_out[12],
    out[11] = NlwRenamedSig_OI_out[11],
    out[10] = NlwRenamedSig_OI_out[10],
    out[9] = NlwRenamedSig_OI_out[9],
    out[8] = NlwRenamedSig_OI_out[8],
    out[7] = NlwRenamedSig_OI_out[7],
    out[6] = NlwRenamedSig_OI_out[6],
    out[5] = NlwRenamedSig_OI_out[5],
    out[4] = NlwRenamedSig_OI_out[4],
    out[3] = NlwRenamedSig_OI_out[3],
    out[2] = NlwRenamedSig_OI_out[2],
    out[1] = NlwRenamedSig_OI_out[1],
    out[0] = NlwRenamedSig_OI_out[0],
    dout[7] = NlwRenamedSig_OI_dout[7],
    dout[6] = NlwRenamedSig_OI_dout[6],
    dout[5] = NlwRenamedSig_OI_dout[5],
    dout[4] = NlwRenamedSig_OI_dout[4],
    dout[3] = NlwRenamedSig_OI_dout[3],
    dout[2] = NlwRenamedSig_OI_dout[2],
    dout[1] = NlwRenamedSig_OI_dout[1],
    dout[0] = NlwRenamedSig_OI_dout[0];
  X_XOR2 sum_Madd__n0000_inst_sum_14 (
    .I0(sum_Madd__n0000_inst_lut2_14),
    .I1(sum_Madd__n0000_inst_cy_13),
    .O(sum__n0000[14])
  );
  X_MUX2 sum_Madd__n0000_inst_cy_14_0 (
    .IB(sum_Madd__n0000_inst_cy_13),
    .IA(fre_cont[14]),
    .SEL(sum_Madd__n0000_inst_lut2_14),
    .O(sum_Madd__n0000_inst_cy_14)
  );
  defparam sum_Madd__n0000_inst_lut2_141.INIT = 4'h6;
  X_LUT2 sum_Madd__n0000_inst_lut2_141 (
    .ADR0(fre_cont[14]),
    .ADR1(sum[14]),
    .O(sum_Madd__n0000_inst_lut2_14)
  );
  X_XOR2 sum_Madd__n0000_inst_sum_13 (
    .I0(sum_Madd__n0000_inst_lut2_13),
    .I1(sum_Madd__n0000_inst_cy_12),
    .O(sum__n0000[13])
  );
  X_MUX2 sum_Madd__n0000_inst_cy_13_1 (
    .IB(sum_Madd__n0000_inst_cy_12),
    .IA(fre_cont[13]),
    .SEL(sum_Madd__n0000_inst_lut2_13),
    .O(sum_Madd__n0000_inst_cy_13)
  );
  X_XOR2 sum_Madd__n0000_inst_sum_12 (
    .I0(sum_Madd__n0000_inst_lut2_12),
    .I1(sum_Madd__n0000_inst_cy_11),
    .O(sum__n0000[12])
  );
  X_MUX2 sum_Madd__n0000_inst_cy_12_2 (
    .IB(sum_Madd__n0000_inst_cy_11),
    .IA(fre_cont[12]),
    .SEL(sum_Madd__n0000_inst_lut2_12),
    .O(sum_Madd__n0000_inst_cy_12)
  );
  X_XOR2 sum_Madd__n0000_inst_sum_11 (
    .I0(sum_Madd__n0000_inst_lut2_11),
    .I1(sum_Madd__n0000_inst_cy_10),
    .O(sum__n0000[11])
  );
  X_MUX2 sum_Madd__n0000_inst_cy_11_3 (
    .IB(sum_Madd__n0000_inst_cy_10),
    .IA(fre_cont[11]),
    .SEL(sum_Madd__n0000_inst_lut2_11),
    .O(sum_Madd__n0000_inst_cy_11)
  );
  X_XOR2 sum_Madd__n0000_inst_sum_10 (
    .I0(sum_Madd__n0000_inst_lut2_10),
    .I1(sum_Madd__n0000_inst_cy_9),
    .O(sum__n0000[10])
  );
  X_MUX2 sum_Madd__n0000_inst_cy_10_4 (
    .IB(sum_Madd__n0000_inst_cy_9),
    .IA(fre_cont[10]),
    .SEL(sum_Madd__n0000_inst_lut2_10),
    .O(sum_Madd__n0000_inst_cy_10)
  );
  X_XOR2 sum_Madd__n0000_inst_sum_9 (
    .I0(sum_Madd__n0000_inst_lut2_9),
    .I1(sum_Madd__n0000_inst_cy_8),
    .O(sum__n0000[9])
  );
  X_MUX2 sum_Madd__n0000_inst_cy_9_5 (
    .IB(sum_Madd__n0000_inst_cy_8),
    .IA(fre_cont[9]),
    .SEL(sum_Madd__n0000_inst_lut2_9),
    .O(sum_Madd__n0000_inst_cy_9)
  );
  X_XOR2 sum_Madd__n0000_inst_sum_8 (
    .I0(sum_Madd__n0000_inst_lut2_8),
    .I1(sum_Madd__n0000_inst_cy_7),
    .O(sum__n0000[8])
  );
  X_MUX2 sum_Madd__n0000_inst_cy_8_6 (
    .IB(sum_Madd__n0000_inst_cy_7),
    .IA(fre_cont[8]),
    .SEL(sum_Madd__n0000_inst_lut2_8),
    .O(sum_Madd__n0000_inst_cy_8)
  );
  X_XOR2 sum_Madd__n0000_inst_sum_7 (
    .I0(sum_Madd__n0000_inst_lut2_7),
    .I1(sum_Madd__n0000_inst_cy_6),
    .O(sum__n0000[7])
  );
  X_MUX2 sum_Madd__n0000_inst_cy_7_7 (
    .IB(sum_Madd__n0000_inst_cy_6),
    .IA(fre_cont[7]),
    .SEL(sum_Madd__n0000_inst_lut2_7),
    .O(sum_Madd__n0000_inst_cy_7)
  );
  X_XOR2 sum_Madd__n0000_inst_sum_6 (
    .I0(sum_Madd__n0000_inst_lut2_6),
    .I1(sum_Madd__n0000_inst_cy_5),
    .O(sum__n0000[6])
  );
  X_MUX2 sum_Madd__n0000_inst_cy_6_8 (
    .IB(sum_Madd__n0000_inst_cy_5),
    .IA(fre_cont[6]),
    .SEL(sum_Madd__n0000_inst_lut2_6),
    .O(sum_Madd__n0000_inst_cy_6)
  );
  X_XOR2 sum_Madd__n0000_inst_sum_5 (
    .I0(sum_Madd__n0000_inst_lut2_5),
    .I1(sum_Madd__n0000_inst_cy_4