armtst_translate.v

Verilog编程

// Xilinx Verilog netlist produced by netgen application (version G.26)
// Command      : -intstyle ise -w -ofmt verilog -sim armtst.ngd armtst_translate.v 
// Input file   : armtst.ngd
// Output file  : armtst_translate.v
// Design name  : armtst
// # of Modules : 1
// Xilinx       : C:/Xilinx
// Device       : 3s400pq208-4

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module armtst (
  NCS3_n, clkin, rst, NWE_n, clk_out, addr, DataIN, out, dout
);
  input NCS3_n;
  input clkin;
  input rst;
  input NWE_n;
  output clk_out;
  input [4 : 0] addr;
  input [15 : 0] DataIN;
  output [15 : 0] out;
  output [7 : 0] dout;
  wire clk_out_OBUF;
  wire ram_data_2_2;
  wire NCS3_n_IBUF;
  wire rst_IBUF;
  wire ram_data_2_3;
  wire NWE_n_BUFGP;
  wire ram_data_2_0;
  wire ram_data_2_1;
  wire _n0193;
  wire ram_data_1_15;
  wire sum_Madd__n0000_inst_lut2_4;
  wire ram_data_1_14;
  wire _n0186;
  wire sum_Madd__n0000_inst_cy_1;
  wire _n0191;
  wire _n0187;
  wire _n0188;
  wire _n0192;
  wire sum_Madd__n0000_inst_lut2_1;
  wire sum_Madd__n0000_inst_lut2_0;
  wire _n0185;
  wire sum_Madd__n0000_inst_cy_2;
  wire _n0184;
  wire _n0190;
  wire sum_Madd__n0000_inst_lut2_9;
  wire sum_Madd__n0000_inst_lut2_7;
  wire ram_data_1_12;
  wire Mmux__COND_1__net35;
  wire _n0178;
  wire ram_data_3_12;
  wire _n0183;
  wire _n0179;
  wire Mmux__COND_1__net34;
  wire ram_data_2_6;
  wire sum_Madd__n0000_inst_lut2_8;
  wire _n0177;
  wire _n0182;
  wire sum_Madd__n0000_inst_cy_9;
  wire _n0176;
  wire CLKDV_OUT;
  wire CLK0;
  wire _n0181;
  wire ram_data_2_15;
  wire ram_data_1_13;
  wire ram_data_2_5;
  wire ram_data_28_2;
  wire ram_data_31_7;
  wire ram_data_28_5;
  wire ram_data_28_4;
  wire ram_data_31_8;
  wire ram_data_28_7;
  wire ram_data_31_10;
  wire ram_data_3_15;
  wire ram_data_4_0;
  wire ram_data_4_1;
  wire ram_data_4_2;
  wire ram_data_4_3;
  wire ram_data_4_4;
  wire ram_data_4_5;
  wire ram_data_4_6;
  wire ram_data_4_7;
  wire ram_data_4_8;
  wire ram_data_4_9;
  wire ram_data_4_10;
  wire ram_data_4_11;
  wire ram_data_4_12;
  wire ram_data_4_13;
  wire ram_data_4_14;
  wire ram_data_4_15;
  wire ram_data_5_0;
  wire ram_data_5_1;
  wire ram_data_5_2;
  wire ram_data_5_3;
  wire ram_data_5_4;
  wire ram_data_5_5;
  wire ram_data_5_6;
  wire ram_data_5_7;
  wire ram_data_5_8;
  wire ram_data_5_9;
  wire ram_data_5_10;
  wire ram_data_5_11;
  wire ram_data_5_12;
  wire ram_data_3_13;
  wire ram_data_3_14;
  wire ram_data_28_6;
  wire ram_data_28_11;
  wire ram_data_31_9;
  wire ram_data_28_10;
  wire ram_data_28_9;
  wire ram_data_31_11;
  wire ram_data_28_8;
  wire ram_data_28_13;
  wire ram_data_26_14;
  wire ram_data_28_12;
  wire ram_data_29_1;
  wire ram_data_26_13;
  wire ram_data_30_13;
  wire ram_data_31_12;
  wire ram_data_29_0;
  wire ram_data_26_12;
  wire ram_data_27_1;
  wire ram_data_28_15;
  wire ram_data_31_14;
  wire ram_data_30_12;
  wire ram_data_27_0;
  wire ram_data_28_14;
  wire ram_data_29_3;
  wire ram_data_26_15;
  wire ram_data_30_14;
  wire ram_data_31_13;
  wire ram_data_29_2;
  wire ram_data_27_3;
  wire ram_data_31_0;
  wire ram_data_31_15;
  wire ram_data_29_6;
  wire ram_data_27_2;
  wire ram_data_27_7;
  wire ram_data_29_5;
  wire ram_data_0_1;
  wire ram_data_30_15;
  wire ram_data_27_6;
  wire ram_data_29_4;
  wire ram_data_29_9;
  wire ram_data_27_5;
  wire ram_data_31_1;
  wire ram_data_0_0;
  wire ram_data_29_8;
  wire ram_data_27_4;
  wire ram_data_27_9;
  wire ram_data_29_7;
  wire ram_data_0_2;
  wire ram_data_27_8;
  wire ram_data_27_13;
  wire ram_data_29_11;
  wire ram_data_0_4;
  wire ram_data_31_2;
  wire ram_data_27_12;
  wire ram_data_29_10;
  wire ram_data_29_15;
  wire ram_data_27_11;
  wire ram_data_31_4;
  wire ram_data_0_3;
  wire ram_data_29_14;
  wire ram_data_27_10;
  wire ram_data_27_15;
  wire ram_data_29_13;
  wire ram_data_0_5;
  wire ram_data_31_3;
  wire ram_data_27_14;
  wire ram_data_29_12;
  wire ram_data_30_1;
  wire Mmux__COND_1__net36;
  wire ram_data_31_5;
  wire ram_data_30_0;
  wire ram_data_30_5;
  wire Mmux__COND_1__net33;
  wire ram_data_28_1;
  wire ram_data_0_6;
  wire ram_data_30_4;
  wire ram_data_1_11;
  wire ram_data_28_0;
  wire ram_data_30_3;
  wire ram_data_0_8;
  wire sum_Madd__n0000_inst_cy_7;
  wire ram_data_31_6;
  wire ram_data_30_2;
  wire ram_data_30_7;
  wire sum_Madd__n0000_inst_cy_0;
  wire ram_data_28_3;
  wire ram_data_0_7;
  wire ram_data_30_6;
  wire ram_data_3_11;
  wire sum_Madd__n0000_inst_lut2_15;
  wire ram_data_0_9;
  wire ram_data_30_10;
  wire sum_Madd__n0000_inst_cy_13;
  wire _n0189;
  wire ram_data_30_9;
  wire fre_cont_N620;
  wire ram_data_2_4;
  wire sum_Madd__n0000_inst_cy_14;
  wire ram_data_30_8;
  wire _n0162;
  wire sum_Madd__n0000_inst_lut2_13;
  wire sum_Madd__n0000_inst_cy_6;
  wire ram_data_0_10;
  wire _n0163;
  wire sum_Madd__n0000_inst_lut2_2;
  wire sum_Madd__n0000_inst_lut2_14;
  wire ram_data_30_11;
  wire _n0164;
  wire sum_Madd__n0000_inst_cy_3;
  wire sum_Madd__n0000_inst_cy_12;
  wire _n0165;
  wire _n0170;
  wire sum_Madd__n0000_inst_lut2_11;
  wire sum_Madd__n0000_inst_lut2_5;
  wire _n0166;
  wire _n0171;
  wire ram_data_3_9;
  wire sum_Madd__n0000_inst_lut2_12;
  wire _n0167;
  wire _n0172;
  wire sum_Madd__n0000_inst_cy_10;
  wire ram_data_3_10;
  wire _n0168;
  wire _n0173;
  wire sum_Madd__n0000_inst_cy_4;
  wire sum_Madd__n0000_inst_cy_11;
  wire _n0169;
  wire _n0174;
  wire sum_Madd__n0000_inst_lut2_3;
  wire sum_Madd__n0000_inst_lut2_10;
  wire _n0175;
  wire _n0180;
  wire sum_Madd__n0000_inst_cy_8;
  wire ram_data_3_0;
  wire dout_7_OBUF;
  wire dout_6_OBUF;
  wire dout_5_OBUF;
  wire dout_4_OBUF;
  wire dout_3_OBUF;
  wire dout_2_OBUF;
  wire dout_1_OBUF;
  wire dout_0_OBUF;
  wire addr_4_IBUF;
  wire addr_3_IBUF;
  wire addr_2_IBUF;
  wire addr_1_IBUF;
  wire addr_0_IBUF;
  wire DataIN_15_IBUF;
  wire DataIN_14_IBUF;
  wire DataIN_13_IBUF;
  wire DataIN_12_IBUF;
  wire DataIN_11_IBUF;
  wire DataIN_10_IBUF;
  wire DataIN_9_IBUF;
  wire DataIN_8_IBUF;
  wire DataIN_7_IBUF;
  wire DataIN_6_IBUF;
  wire DataIN_5_IBUF;
  wire DataIN_4_IBUF;
  wire DataIN_3_IBUF;
  wire DataIN_2_IBUF;
  wire DataIN_1_IBUF;
  wire DataIN_0_IBUF;
  wire ram_data_0_11;
  wire ram_data_0_12;
  wire ram_data_0_13;
  wire ram_data_0_14;
  wire ram_data_0_15;
  wire ram_data_1_0;
  wire ram_data_1_1;
  wire ram_data_1_2;
  wire ram_data_2_7;
  wire ram_data_2_8;
  wire ram_data_2_9;
  wire ram_data_2_10;
  wire ram_data_2_11;
  wire ram_data_2_12;
  wire ram_data_2_13;
  wire ram_data_2_14;
  wire ram_data_1_3;
  wire ram_data_1_4;
  wire ram_data_1_5;
  wire ram_data_1_6;
  wire ram_data_1_7;
  wire ram_data_1_8;
  wire ram_data_1_9;
  wire ram_data_1_10;
  wire ram_data_3_1;
  wire ram_data_3_2;
  wire ram_data_3_3;
  wire ram_data_3_4;
  wire ram_data_3_5;
  wire ram_data_3_6;
  wire ram_data_3_7;
  wire ram_data_3_8;
  wire ram_data_5_13;
  wire ram_data_5_14;
  wire ram_data_5_15;
  wire ram_data_6_0;
  wire ram_data_6_1;
  wire ram_data_6_2;
  wire ram_data_6_3;
  wire ram_data_6_4;
  wire ram_data_6_5;
  wire ram_data_6_6;
  wire ram_data_6_7;
  wire ram_data_6_8;
  wire ram_data_6_9;
  wire ram_data_6_10;
  wire ram_data_6_11;
  wire ram_data_6_12;
  wire ram_data_6_13;
  wire ram_data_6_14;
  wire ram_data_6_15;
  wire ram_data_7_0;
  wire ram_data_7_1;
  wire ram_data_7_2;
  wire ram_data_7_3;
  wire ram_data_7_4;
  wire ram_data_7_5;
  wire ram_data_7_6;
  wire ram_data_7_7;
  wire ram_data_7_8;
  wire ram_data_7_9;
  wire ram_data_7_10;
  wire ram_data_7_11;
  wire ram_data_7_12;
  wire ram_data_7_13;
  wire ram_data_7_14;
  wire ram_data_7_15;
  wire ram_data_8_0;
  wire ram_data_8_1;
  wire ram_data_8_2;
  wire ram_data_8_3;
  wire ram_data_8_4;
  wire ram_data_8_5;
  wire ram_data_8_6;
  wire ram_data_8_7;
  wire ram_data_8_8;
  wire ram_data_8_9;
  wire ram_data_8_10;
  wire ram_data_8_11;
  wire ram_data_8_12;
  wire ram_data_8_13;
  wire ram_data_8_14;
  wire ram_data_8_15;
  wire ram_data_9_0;
  wire ram_data_9_1;
  wire ram_data_9_2;
  wire ram_data_9_3;
  wire ram_data_9_4;
  wire ram_data_9_5;
  wire ram_data_9_6;
  wire ram_data_9_7;
  wire ram_data_9_8;
  wire ram_data_9_9;
  wire ram_data_9_10;
  wire ram_data_9_11;
  wire ram_data_9_12;
  wire ram_data_9_13;
  wire ram_data_9_14;
  wire ram_data_9_15;
  wire ram_data_10_0;
  wire ram_data_10_1;
  wire ram_data_10_2;
  wire ram_data_10_3;
  wire ram_data_10_4;
  wire ram_data_10_5;
  wire ram_data_10_6;
  wire ram_data_10_7;
  wire ram_data_10_8;
  wire ram_data_10_9;
  wire ram_data_10_10;
  wire ram_data_10_11;
  wire ram_data_10_12;
  wire ram_data_10_13;
  wire ram_data_10_14;
  wire ram_data_10_15;
  wire ram_data_11_0;
  wire ram_data_11_1;
  wire ram_data_11_2;
  wire ram_data_11_3;
  wire ram_data_11_4;
  wire ram_data_11_5;
  wire ram_data_11_6;
  wire ram_data_11_7;
  wire ram_data_11_8;
  wire ram_data_11_9;
  wire ram_data_11_10;
  wire ram_data_11_11;
  wire ram_data_11_12;
  wire ram_data_11_13;
  wire ram_data_11_14;
  wire ram_data_11_15;
  wire ram_data_12_0;
  wire ram_data_12_1;
  wire ram_data_12_2;
  wire ram_data_12_3;
  wire ram_data_12_4;
  wire ram_data_12_5;
  wire ram_data_12_6;
  wire ram_data_12_7;
  wire ram_data_12_8;
  wire ram_data_12_9;
  wire ram_data_12_10;
  wire ram_data_12_11;
  wire ram_data_12_12;
  wire ram_data_12_13;
  wire ram_data_12_14;
  wire ram_data_12_15;
  wire ram_data_13_0;
  wire ram_data_13_1;
  wire ram_data_13_2;
  wire ram_data_13_3;
  wire ram_data_13_4;
  wire ram_data_13_5;
  wire ram_data_13_6;
  wire ram_data_13_7;
  wire ram_data_13_8;
  wire ram_data_13_9;
  wire ram_data_13_10;
  wire ram_data_13_11;
  wire ram_data_13_12;
  wire ram_data_13_13;
  wire ram_data_13_14;
  wire ram_data_13_15;
  wire ram_data_14_0;
  wire ram_data_14_1;
  wire ram_data_14_2;
  wire ram_data_14_3;
  wire ram_data_14_4;
  wire ram_data_14_5;
  wire ram_data_14_6;
  wire ram_data_14_7;
  wire ram_data_14_8;