📄 top.bld

📁 Verilog编程
💻 BLD
字号:
Release 6.1.03i - ngdbuild G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -intstyle ise -dd d:\商共享资料\程序\两路正弦波/_ngo -uc
top_ucf.ucf -p xc3s400-pq208-4 top.ngc top.ngd Reading NGO file "D:/商共享资料/程序/两路正弦波/top.ngc" ...Reading component libraries for design expansion...Launcher: "rom1.ngo" is up to date.Loading design module "d:\商共享资料\程序\两路正弦波\_ngo\rom1.ngo"...blkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iAnnotating constraints to design from file "top_ucf.ucf" ...Attached a PULLUP primitive to pad net NWE_n Attached a PULLDOWN primitive to pad net rst Attached a PULLUP primitive to pad net NCS0_n Attached a PULLDOWN primitive to pad net DataIN<15> Attached a PULLDOWN primitive to pad net DataIN<14> Attached a PULLDOWN primitive to pad net DataIN<13> Attached a PULLDOWN primitive to pad net DataIN<12> Attached a PULLDOWN primitive to pad net DataIN<11> Attached a PULLDOWN primitive to pad net DataIN<10> Attached a PULLDOWN primitive to pad net DataIN<9> Attached a PULLDOWN primitive to pad net DataIN<8> Attached a PULLDOWN primitive to pad net DataIN<7> Attached a PULLDOWN primitive to pad net DataIN<6> Attached a PULLDOWN primitive to pad net DataIN<5> Attached a PULLDOWN primitive to pad net DataIN<4> Attached a PULLDOWN primitive to pad net DataIN<3> Attached a PULLDOWN primitive to pad net DataIN<2> Attached a PULLDOWN primitive to pad net DataIN<1> Attached a PULLDOWN primitive to pad net DataIN<0> Attached a PULLUP primitive to pad net clk_out1 Attached a PULLUP primitive to pad net clk_out2 Attached a PULLUP primitive to pad net clk_out3 Attached a PULLUP primitive to pad net clk_out4 Attached a PULLUP primitive to pad net clk_out5 Attached a PULLUP primitive to pad net clk_out6 Attached a PULLDOWN primitive to pad net SINE2<10> Attached a PULLDOWN primitive to pad net SINE2<9> Attached a PULLDOWN primitive to pad net SINE2<8> Attached a PULLDOWN primitive to pad net SINE2<7> Attached a PULLDOWN primitive to pad net SINE2<6> Attached a PULLDOWN primitive to pad net SINE2<5> Attached a PULLDOWN primitive to pad net SINE2<4> Attached a PULLDOWN primitive to pad net SINE2<3> Attached a PULLDOWN primitive to pad net SINE2<2> Attached a PULLDOWN primitive to pad net SINE2<1> Attached a PULLDOWN primitive to pad net SINE2<0> Checking timing specifications ...Checking expanded design ...WARNING:NgdBuild:477 - clock net 'CLKDV_OUT' has non-clock connections. These
   problematic connections include:     pin I0 on block clk_out51 with type LUT1NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   1Total memory usage is 47072 kilobytesWriting NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -