fifo_asyn.xco

Verilog编程

# Xilinx CORE Generator 6.1.03i
# Username = 丁伟森
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = E:\ise6.1\tst
# ExpandedProjectPath = E:\ise6.1\tst
# OverwriteFiles = true
# Core name: fifo_asyn
# Number of Primitives in design: 171
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 58
# Number of LUTs used in design: 58
# Number of REG used in design: 60
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 1
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan3
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Asynchronous_FIFO Spartan3 Xilinx,_Inc. 5.1
CSET read_error_sense = active_high
CSET read_count_width = 2
CSET write_acknowledge = false
CSET create_rpm = false
CSET read_acknowledge = false
CSET read_count = false
CSET write_error = false
CSET almost_full_flag = false
CSET almost_empty_flag = false
CSET memory_type = block
CSET read_error = false
CSET fifo_depth = 255
CSET component_name = fifo_asyn
CSET input_data_width = 16
CSET write_count = false
CSET write_acknowledge_sense = active_high
CSET read_acknowledge_sense = active_high
CSET write_error_sense = active_high
CSET write_count_width = 2
GENERATE