rom.edn

Verilog编程

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 5 3 10 16 53)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.1i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2003 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_sinit_value = 0 ")
       (comment "c_has_en = 0 ")
       (comment "c_reg_inputs = 0 ")
       (comment "c_yclk_is_rising = 1 ")
       (comment "c_ysinit_is_high = 1 ")
       (comment "c_ywe_is_high = 1 ")
       (comment "c_yprimitive_type = 16kx1 ")
       (comment "c_ytop_addr = 1024 ")
       (comment "c_yhierarchy = hierarchy1 ")
       (comment "c_has_limit_data_pitch = 0 ")
       (comment "c_has_rdy = 0 ")
       (comment "c_write_mode = 2 ")
       (comment "c_width = 14 ")
       (comment "c_yuse_single_primitive = 0 ")
       (comment "c_has_nd = 0 ")
       (comment "c_has_we = 0 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_has_rfd = 0 ")
       (comment "c_has_din = 0 ")
       (comment "c_ybottom_addr = 0 ")
       (comment "c_pipe_stages = 0 ")
       (comment "c_yen_is_high = 1 ")
       (comment "c_family = spartan3 ")
       (comment "InstanceName = rom ")
       (comment "c_depth = 16384 ")
       (comment "c_has_default_data = 1 ")
       (comment "c_limit_data_pitch = 18 ")
       (comment "c_has_sinit = 0 ")
       (comment "c_mem_init_file = mif_file_16_1 ")
       (comment "c_default_data = 0 ")
       (comment "c_ymake_bmm = 0 ")
       (comment "c_addr_width = 14 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell LUT3 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXF5 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXF6 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell RAMB16_S1 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port WE (direction INPUT))
                   (port EN (direction INPUT))
                   (port SSR (direction INPUT))
                   (port CLK (direction INPUT))
                   (port (rename DI_0_ "DI<0>") (direction INPUT))
                   (port (rename DO_0_ "DO<0>") (direction OUTPUT))
                   (port (rename ADDR_0_ "ADDR<0>") (direction INPUT))
                   (port (rename ADDR_1_ "ADDR<1>") (direction INPUT))
                   (port (rename ADDR_2_ "ADDR<2>") (direction INPUT))
                   (port (rename ADDR_3_ "ADDR<3>") (direction INPUT))
                   (port (rename ADDR_4_ "ADDR<4>") (direction INPUT))
                   (port (rename ADDR_5_ "ADDR<5>") (direction INPUT))
                   (port (rename ADDR_6_ "ADDR<6>") (direction INPUT))
                   (port (rename ADDR_7_ "ADDR<7>") (direction INPUT))
                   (port (rename ADDR_8_ "ADDR<8>") (direction INPUT))
                   (port (rename ADDR_9_ "ADDR<9>") (direction INPUT))
                   (port (rename ADDR_10_ "ADDR<10>") (direction INPUT))
                   (port (rename ADDR_11_ "ADDR<11>") (direction INPUT))
                   (port (rename ADDR_12_ "ADDR<12>") (direction INPUT))
                   (port (rename ADDR_13_ "ADDR<13>") (direction INPUT))