tst1.bld

Verilog编程

Release 6.1i - ngdbuild G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -intstyle ise -dd e:\fpga_program\ise6.1\tst/_ngo -uc
tst1_ucf.ucf -p xc3s400-pq208-4 TST1.ngc TST1.ngd 

Reading NGO file "E:/fpga_program/ise6.1/tst/TST1.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "tst1_ucf.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40764 kilobytes

Writing NGD file "TST1.ngd" ...

Writing NGDBUILD log file "TST1.bld"...