counter.v

Verilog编程

module counter(rst,inclk,outclk,clkdata);
	input rst,inclk;
	input[25:0] clkdata;
	output outclk;

	reg outclktemp;
	reg[25:0] cout;	 
	 assign outclk=(clkdata>=2)?outclktemp:inclk;

	initial 
	begin
		cout = 0;
	end

	always @(posedge inclk or posedge rst)
			begin 			
			if(rst)
				begin
					cout<=16'h0000;
					outclktemp<=1'b0;
				end
			else
				begin
				  
					if(clkdata>=16'h0002)
						begin
							if(cout>=clkdata-1)
								begin
									outclktemp<=1'b0;
									cout<=16'h0000;
								end
							else if(cout>=((clkdata>>1)-1))
								begin
									cout<=cout+1;
									outclktemp<=1'b1;
								end
							else
								begin
									outclktemp<=1'b0;
								  	cout<=cout+1;
								end
						 end
				end
	  end
endmodule