fifo_asyn.xcp

来自「Verilog编程」· XCP 代码 · 共 23 行

# Xilinx CORE Generator 6.1.03i
SELECT Asynchronous_FIFO Spartan3 Xilinx,_Inc. 5.1
CSET read_error_sense = active_high
CSET read_count_width = 2
CSET write_acknowledge = false
CSET create_rpm = false
CSET read_acknowledge = false
CSET read_count = false
CSET write_error = false
CSET almost_full_flag = false
CSET almost_empty_flag = false
CSET memory_type = block
CSET read_error = false
CSET fifo_depth = 255
CSET component_name = fifo_asyn
CSET input_data_width = 16
CSET write_count = false
CSET write_acknowledge_sense = active_high
CSET read_acknowledge_sense = active_high
CSET write_error_sense = active_high
CSET write_count_width = 2
GENERATE