tst.npl

Verilog编程

JDF G
// Created by Project Navigator ver 1.0
PROJECT tst
DESIGN tst
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s400
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE top.v
SOURCE dds4.v
SOURCE DDS1.v
SOURCE counter.v
SOURCE my_dcm1.xaw
SOURCE rom1.xco
STIMULUS dds_tbw.tbw
STIMULUS counter_tbw.tbw
STIMULUS top_tbw.tbw
STIMULUS ding_tbw.tbw
DEPASSOC top top_ucf.ucf
DEPASSOC DDS1 DDS1.ucf
[STATUS-ALL]
DDS1.ngcFile=WARNINGS,1208919503
[STRATEGY-LIST]
Normal=True