armtst.mrp

Verilog编程

Release 6.1i Map G.26
Xilinx Mapping Report File for Design 'armtst'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc3s400-pq208-4 -cm
area -pr b -k 4 -c 100 -tx off -o armtst_map.ncd armtst.ngd armtst.pcf 
Target Device  : x3s400
Target Package : pq208
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.16 $
Mapped Date    : Sat Apr 28 19:32:56 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:   17
Logic Utilization:
  Number of Slice Flip Flops:         512 out of   7,168    7%
  Number of 4 input LUTs:             325 out of   7,168    4%
Logic Distribution:
  Number of occupied Slices:                          404 out of   3,584   11%
    Number of Slices containing only related logic:     404 out of     404  100%
    Number of Slices containing unrelated logic:          0 out of     404    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         325 out of   7,168    4%
  Number of bonded IOBs:               41 out of     141   29%
    IOB Flip Flops:                    16
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  13,900
Additional JTAG gate count for IOBs:  1,968
Peak Memory Usage:  77 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT - Resistive elements (PULLUP/PULLDOWN/KEEPER) on Clock net driving
   IBUFG symbol "NWE_n_BUFGP/IBUFG" (output signal=NWE_n_BUFGP/IBUFG) will be
   ignored.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   out<10> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   out<11> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   out<12> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   out<13> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   out<14> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   out<15> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<0>
   is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<1>
   is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<2>
   is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<3>
   is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<4>
   is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<5>
   is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<6>
   is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<7>
   is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<8>
   is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp out<9>
   is set but TMUX is not configured.

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "NWE_n_BUFGP" (output signal=NWE_n_BUFGP),
   BUFG symbol "instance_name_CLK0_BUFG_INST" (output signal=CLK0)

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) removed
   1 block(s) optimized away
   2 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

Loadless block "instance_name_CLK180_BUFG_INST" (CKBUF) removed.
 The signal "instance_name_CLK180_BUF" is loadless and has been removed.
Loadless block "instance_name_CLKFX_BUFG_INST" (CKBUF) removed.
 The signal "instance_name_CLKFX_BUF" is loadless and has been removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| DataIN<0>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<1>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<2>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<3>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<4>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<5>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<6>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<7>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<8>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<9>                          | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<10>                         | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<11>                         | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<12>                         | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<13>                         | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<14>                         | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| DataIN<15>                         | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
| NCS3_n                             | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLUP   |       |
| NWE_n                              | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLUP   |       |
| addr<0>                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| addr<1>                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| addr<2>                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| addr<3>                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| addr<4>                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| clkin                              | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| out<0>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<1>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<2>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<3>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<4>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<5>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<6>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<7>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<8>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<9>                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<10>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<11>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<12>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<13>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<14>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| out<15>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     | PULLDOWN |       |
| rst                                | IOB     | INPUT     | LVCMOS25    |          |      |          | PULLDOWN |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 41
Number of Equivalent Gates for Design = 13,900
Number of RPM Macros = 0
Number of Hard Macros = 0
DCIRESETs = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
DCMs = 1
GCLKs = 2
ICAPs = 0
18X18 Multipliers = 0
Block RAMs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 16
IOB Dual-Rate Flops not driven by LUTs = 0
IOB Dual-Rate Flops = 0
IOB Slave Pads = 0
IOB Master Pads = 0
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 16
IOB Flip Flops = 16
Unbonded IOBs = 0
Bonded IOBs = 41
Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MUXFXs = 240
MULTANDs = 0
4 input LUTs used as Route-Thrus = 0
4 input LUTs = 325
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 0
Slice Flip Flops = 512
SliceMs = 64
SliceLs = 340
Slices = 404
Number of LUT signals with 4 loads = 0
Number of LUT signals with 3 loads = 0
Number of LUT signals with 2 loads = 0
Number of LUT signals with 1 load = 256
NGM Average fanout of LUT = 4.85
NGM Maximum fanout of LUT = 265
NGM Average fanin for LUT = 3.0800
Number of LUT symbols = 325
Number of IPAD symbols = 25
Number of IBUF symbols = 25
Number of DCM symbols = 1