dds4.bld

来自「Verilog编程」· BLD 代码 · 共 30 行

BLD
30 行
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Release 6.1i - ngdbuild G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -intstyle ise -dd e:\fpga_program\ise6.1\tst/_ngo -i -p
xc3s400-pq208-4 dds4.ngc dds4.ngd Reading NGO file "E:/fpga_program/ise6.1/tst/dds4.ngc" ...Reading component libraries for design expansion...Launcher: "rom1.ngo" is up to date.Loading design module "e:\fpga_program\ise6.1\tst\_ngo\rom1.ngo"...blkmemsp_v5_0, Coregen 6.1.03iblkmemsp_v5_0, Coregen 6.1.03iblkmemsp_v5_0, Coregen 6.1.03iblkmemsp_v5_0, Coregen 6.1.03iblkmemsp_v5_0, Coregen 6.1.03iblkmemsp_v5_0, Coregen 6.1.03iChecking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Total memory usage is 43836 kilobytesWriting NGD file "dds4.ngd" ...Writing NGDBUILD log file "dds4.bld"...

dds4.bld - 源码说明

本页面展示了「Verilog编程」中的 dds4.bld 源码文件，采用 BLD 编程语言编写，共 30 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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