armtst.v

Verilog编程

module armtst(clkin,
			  rst,
			  
			 	 
           NCS3_n,
			  NWE_n,
			  addr,
			  DataIN,
						  
			  out,
			  dout,
			  clk_out
			  		  
          	);

input clkin;              //50M clock;
input rst;



input NCS3_n;
input NWE_n;            //
input [4:0] addr;
input [15:0] DataIN;
   
                    
output [15:0]out;
output [7:0] dout;
output clk_out; 



wire CLKDV_OUT;




my_dcm1 instance_name (
    .LOCKED_OUT(), 
    .CLKIN_IN(clkin), 
    .CLK180_OUT(), 
    .CLKFX_OUT(CLKDV_OUT), 			// 输入时钟50M，输出50M
    .CLK0_OUT(CLK0), 
    .CLKIN_IBUFG_OUT()
    );




reg [15:0] CONTROL;


parameter wordwidth_data=16,memsize_data=32;
reg [wordwidth_data-1:0] ram_data [memsize_data-1:0];

always @(posedge NWE_n  or posedge rst)

if(rst)
begin
ram_data[0]<=16'b1010101101110000;

ram_data[1]<=16'b0000100011110111;
ram_data[2]<=16'b0000100011110111;
ram_data[3]<=16'b0000100011110111;
ram_data[4]<=16'b0000100011110111;
ram_data[5]<=16'b0000100011110111;
ram_data[6]<=16'b0000100011110111;

ram_data[7]<=0;
ram_data[8]<=0;
ram_data[9]<=0;
ram_data[10]<=0;
ram_data[11]<=16'b1000000000000000;
ram_data[12]<=0;

ram_data[13]<=16'b0000011111111111;
ram_data[14]<=0;
ram_data[15]<=0;
ram_data[16]<=0;
ram_data[17]<=0;
ram_data[18]<=0;

ram_data[19]<=0;
ram_data[20]<=0;
ram_data[21]<=0;
ram_data[22]<=0;
ram_data[23]<=0;
ram_data[24]<=0;


ram_data[25]<=0;
ram_data[26]<=0;
ram_data[27]<=0;
ram_data[28]<=0;
ram_data[29]<=0;
ram_data[30]<=0;
ram_data[31]<=0;
end
else if(NCS3_n==0)
      begin
      ram_data[addr]<=DataIN;
      end
     else
      ram_data[addr]<=ram_data[addr];
    
reg [15:0] fre_cont;

always @ (posedge CLK0 or posedge rst)			  //50M时钟

if(rst)
begin
CONTROL<=0;
end
//else if(NCS0_n==1)
else
begin
 CONTROL<=ram_data[0];
 fre_cont<=	ram_data[1];
end 

reg [15:0] sum;

always @(posedge CLK0 or posedge rst)

if(rst)
  sum<=0;
else
  sum<=sum+fre_cont;


rom sin(    .addr(sum[15:8]),
	         .clk(CLKDV_OUT),
	         .dout(dout)
			   );


assign out=CONTROL;
assign clk_out=~CLKDV_OUT;


endmodule