a1.cmd_log

Verilog编程

xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
ngdbuild -intstyle ise -dd e:\fpga_program\ise6.1\tst/_ngo -i  -p xc3s400-pq208-4 a1.ngc a1.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o a1_map.ncd a1.ngd a1.pcf
par -w -intstyle ise -ol std -t 1 a1_map.ncd a1.ncd a1.pcf
trce -intstyle ise -e 3 -l 3 -xml a1 a1.ncd -o a1.twr a1.pcf
bitgen -intstyle ise -f a1.ut a1.ncd
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr
xst -intstyle ise -ifn __projnav/a1.xst -ofn a1.syr