_primary.vhd

来自「Verilog编程」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity rom1 is
    port(
        addr            : in     vl_logic_vector(9 downto 0);
        clk             : in     vl_logic;
        dout            : out    vl_logic_vector(9 downto 0);
        en              : in     vl_logic
    );
end rom1;