_primary.vhd

Verilog编程

library verilog;
use verilog.vl_types.all;
entity my_dcm1 is
    port(
        locked_out      : out    vl_logic;
        clkin_in        : in     vl_logic;
        clk180_out      : out    vl_logic;
        clkfx_out       : out    vl_logic;
        clk0_out        : out    vl_logic;
        clkin_ibufg_out : out    vl_logic
    );
end my_dcm1;