a1.v

Verilog编程

module a1(clk,Aclr,rst,Q);

input clk,rst,Aclr;


output Q;


 reg Q;


always @(posedge clk or posedge rst)

if(rst)
begin
  Q<=1;
  end
else if(	Q==1)
  Q<=Aclr;



endmodule