armtst.par

Verilog编程

Release 6.1i Par G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

DWS::  Sat Apr 28 19:33:05 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 armtst_map.ncd
armtst.ncd armtst.pcf 


Constraints file: armtst.pcf

Loading device database for application Par from file "armtst_map.ncd".
   "armtst" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
C:/Xilinx.
Device speed data version:  PREVIEW 1.27 2003-11-04.


Resolved that IOB <DataIN<0>> must be placed at site P40.
Resolved that IOB <DataIN<1>> must be placed at site P39.
Resolved that IOB <DataIN<2>> must be placed at site P37.
Resolved that IOB <clkin> must be placed at site P79.
Resolved that IOB <DataIN<3>> must be placed at site P36.
Resolved that IOB <DataIN<4>> must be placed at site P35.
Resolved that IOB <DataIN<5>> must be placed at site P34.
Resolved that IOB <DataIN<6>> must be placed at site P33.
Resolved that IOB <DataIN<7>> must be placed at site P31.
Resolved that IOB <DataIN<8>> must be placed at site P29.
Resolved that IOB <DataIN<9>> must be placed at site P28.
Resolved that IOB <addr<0>> must be placed at site P52.
Resolved that IOB <addr<1>> must be placed at site P51.
Resolved that IOB <addr<2>> must be placed at site P50.
Resolved that IOB <addr<3>> must be placed at site P48.
Resolved that IOB <addr<4>> must be placed at site P46.
Resolved that IOB <DataIN<10>> must be placed at site P27.
Resolved that IOB <DataIN<11>> must be placed at site P26.
Resolved that IOB <DataIN<12>> must be placed at site P24.
Resolved that IOB <DataIN<13>> must be placed at site P22.
Resolved that IOB <DataIN<14>> must be placed at site P21.
Resolved that IOB <DataIN<15>> must be placed at site P20.
Resolved that IOB <out<10>> must be placed at site P68.
Resolved that IOB <out<11>> must be placed at site P67.
Resolved that IOB <out<12>> must be placed at site P65.
Resolved that IOB <out<13>> must be placed at site P64.
Resolved that IOB <out<14>> must be placed at site P58.
Resolved that IOB <out<15>> must be placed at site P57.
Resolved that IOB <NWE_n> must be placed at site P63.
Resolved that IOB <out<0>> must be placed at site P90.
Resolved that IOB <out<1>> must be placed at site P87.
Resolved that IOB <out<2>> must be placed at site P86.
Resolved that IOB <NCS3_n> must be placed at site P61.
Resolved that IOB <out<3>> must be placed at site P85.
Resolved that IOB <out<4>> must be placed at site P81.
Resolved that IOB <out<5>> must be placed at site P78.
Resolved that IOB <out<6>> must be placed at site P76.
Resolved that IOB <out<7>> must be placed at site P74.
Resolved that IOB <out<8>> must be placed at site P72.
Resolved that IOB <out<9>> must be placed at site P71.
Resolved that IOB <rst> must be placed at site P101.


Device utilization summary:

   Number of External IOBs            41 out of 141    29%
      Number of LOCed External IOBs   41 out of 41    100%

   Number of Slices                  404 out of 5376    7%
      Number of SLICEMs               64 out of 1792    3%

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989d0f) REAL time: 2 secs 

Phase 3.8
.......
Phase 3.8 (Checksum:9fd2a5) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 3 secs 

Writing design to file armtst.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 2774 unrouted;       REAL time: 4 secs 

Phase 2: 2492 unrouted;       REAL time: 4 secs 

Phase 3: 848 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 8 secs 

Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|              CLK0       |  BUFGMUX0| No   |   17 |  0.008     |  0.429      |
+-------------------------+----------+------+------+------------+-------------+
|       NWE_n_BUFGP       |  BUFGMUX1| No   |  257 |  0.152     |  0.457      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 203


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.378
   The MAXIMUM PIN DELAY IS:                               5.065
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.274

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1157         908         425         260          24           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  70 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file armtst.ncd.


PAR done.