top.syr

Verilog编程

    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'my_dds4_DDS40_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            my_dds4_DDS40_PHA_ACC_t1_0 (FF)
  Destination:       my_dds4_DDS40_PHA_ACC_t1_15 (FF)
  Source Clock:      my_dds4_DDS40_counterclk_outclktemp:Q rising
  Destination Clock: my_dds4_DDS40_counterclk_outclktemp:Q rising

  Data Path: my_dds4_DDS40_PHA_ACC_t1_0 to my_dds4_DDS40_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  my_dds4_DDS40_PHA_ACC_t1_0 (my_dds4_DDS40_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_0 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_1 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_2 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_3 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_4 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_5 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_6 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_7 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_8 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_9 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_10 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_11 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_12 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_13 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_14 (my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  my_dds4_DDS40_PHA_ACC_t1_Madd__n0000_inst_sum_15 (my_dds4_DDS40_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          my_dds4_DDS40_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'my_dds4_DDS30_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            my_dds4_DDS30_PHA_ACC_t1_0 (FF)
  Destination:       my_dds4_DDS30_PHA_ACC_t1_15 (FF)
  Source Clock:      my_dds4_DDS30_counterclk_outclktemp:Q rising
  Destination Clock: my_dds4_DDS30_counterclk_outclktemp:Q rising

  Data Path: my_dds4_DDS30_PHA_ACC_t1_0 to my_dds4_DDS30_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  my_dds4_DDS30_PHA_ACC_t1_0 (my_dds4_DDS30_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_0 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_1 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_2 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_3 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_4 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_5 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_6 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_7 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_8 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_9 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_10 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_11 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_12 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_13 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_14 (my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  my_dds4_DDS30_PHA_ACC_t1_Madd__n0000_inst_sum_15 (my_dds4_DDS30_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          my_dds4_DDS30_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'my_dds4_DDS20_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            my_dds4_DDS20_PHA_ACC_t1_0 (FF)
  Destination:       my_dds4_DDS20_PHA_ACC_t1_15 (FF)
  Source Clock:      my_dds4_DDS20_counterclk_outclktemp:Q rising
  Destination Clock: my_dds4_DDS20_counterclk_outclktemp:Q rising

  Data Path: my_dds4_DDS20_PHA_ACC_t1_0 to my_dds4_DDS20_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  my_dds4_DDS20_PHA_ACC_t1_0 (my_dds4_DDS20_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_0 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_1 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_2 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_3 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_4 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_5 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_6 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_7 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_8 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_9 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_10 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_11 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_12 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_13 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_14 (my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  my_dds4_DDS20_PHA_ACC_t1_Madd__n0000_inst_sum_15 (my_dds4_DDS20_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          my_dds4_DDS20_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'my_dds4_DDS10_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            my_dds4_DDS10_PHA_ACC_t1_0 (FF)
  Destination:       my_dds4_DDS10_PHA_ACC_t1_15 (FF)
  Source Clock:      my_dds4_DDS10_counterclk_outclktemp:Q rising
  Destination Clock: my_dds4_DDS10_counterclk_outclktemp:Q rising

  Data Path: my_dds4_DDS10_PHA_ACC_t1_0 to my_dds4_DDS10_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  my_dds4_DDS10_PHA_ACC_t1_0 (my_dds4_DDS10_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_0 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_1 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_2 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_3 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_4 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_5 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_6 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_7 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_8 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_9 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_10 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_11 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_12 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_13 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_14 (my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  my_dds4_DDS10_PHA_ACC_t1_Madd__n0000_inst_sum_15 (my_dds4_DDS10_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          my_dds4_DDS10_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'NWE_n'
Offset:              7.159ns (Levels of Logic = 7)
  Source:            addr<0> (PAD)
  Destination:       ram_data_7_9 (FF)
  Destination Clock: NWE_n falling

  Data Path: addr<0> to ram_data_7_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           288   1.492   1.409  addr_0_IBUF (addr_0_IBUF)
     LUT3:I0->O            1   0.720   0.000  Mmux__COND_1_inst_lut3_1581 (Mmux__COND_1__net304)
     MUXF5:I0->O           1   0.387   0.000  Mmux__COND_1_inst_mux_f5_79 (Mmux__COND_1__net306)
     MUXF6:I1->O           1   0.563   0.000  Mmux__COND_1_inst_mux_f6_39 (Mmux__COND_1__net307)
     MUXF7:I1->O           1   0.563   0.000  Mmux__COND_1_inst_mux_f7_19 (Mmux__COND_1__net308)
     MUXF8:I1->O           1   0.563   0.240  Mmux__COND_1_inst_mux_f8_9 (_n0281<9>)
     LUT3:I2->O           32   0.720   0.000  Mmux__n0033_Result<9>1 (_n0033<9>)
     FDCE_1:D                  0.502          ram_data_7_9
    ----------------------------------------
    Total                      7.159ns (5.510ns logic, 1.649ns route)
                                       (77.0% logic, 23.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkin'
Offset:              14.183ns (Levels of Logic = 4)
  Source:            my_dds4_DDS10_rom/B5 (RAM)
  Destination:       SINE1<10> (PAD)
  Source Clock:      clkin rising

  Data Path: my_dds4_DDS10_rom/B5 to SINE1<10>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S18:CLK->DO0    1   3.509   0.240  B5 (dout<0>)
     end scope: 'my_dds4_DDS10_rom'
     MULT18X18:A0->P10     1   3.822   0.240  my_dds4_DDS10_Mmult__n0009_inst_mult_0 (my_dds4_DDS10__n0009<10>)
     LUT1:I0->O            1   0.720   0.240  my_dds4_DDS10_Madd__n0005_Result1 (SINE1_10_OBUF)
     OBUF:I->O                 5.412          SINE1_10_OBUF (SINE1<10>)
    ----------------------------------------
    Total                     14.183ns (13.463ns logic, 0.720ns route)
                                       (94.9% logic, 5.1% route)

=========================================================================
CPU : 50.87 / 53.49 s | Elapsed : 51.00 / 54.00 s
 
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Total memory usage is 96472 kilobytes