top.syr

Verilog编程

 Number of BRAMs:                        6  out of     16    37%  
 Number of MULT18X18s:                   6  out of     16    37%  
 Number of GCLKs:                        4  out of      8    50%  
 Number of DCMs:                         1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
NWE_n                              | BUFGP                  | 512   |
clkin                              | instance_name_DCM_INST:CLK0| 952   |
my_dds4_DDS60_counterclk_outclktemp:Q| NONE                   | 16    |
my_dds4_DDS50_counterclk_outclktemp:Q| NONE                   | 16    |
my_dds4_DDS40_counterclk_outclktemp:Q| NONE                   | 16    |
my_dds4_DDS30_counterclk_outclktemp:Q| NONE                   | 16    |
my_dds4_DDS20_counterclk_outclktemp:Q| NONE                   | 16    |
my_dds4_DDS10_counterclk_outclktemp:Q| NONE                   | 16    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.693ns (Maximum Frequency: 93.519MHz)
   Minimum input arrival time before clock: 7.159ns
   Maximum output required time after clock: 14.183ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'NWE_n'
Delay:               5.342ns (Levels of Logic = 6)
  Source:            ram_data_0_9 (FF)
  Destination:       ram_data_7_9 (FF)
  Source Clock:      NWE_n falling
  Destination Clock: NWE_n falling

  Data Path: ram_data_0_9 to ram_data_7_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE_1:C->Q           2   0.619   0.465  ram_data_0_9 (ram_data_0_9)
     LUT3:I1->O            1   0.720   0.000  Mmux__COND_1_inst_lut3_1441 (Mmux__COND_1__net279)
     MUXF5:I0->O           1   0.387   0.000  Mmux__COND_1_inst_mux_f5_72 (Mmux__COND_1__net281)
     MUXF6:I0->O           1   0.563   0.000  Mmux__COND_1_inst_mux_f6_36 (Mmux__COND_1__net285)
     MUXF7:I0->O           1   0.563   0.000  Mmux__COND_1_inst_mux_f7_18 (Mmux__COND_1__net293)
     MUXF8:I0->O           1   0.563   0.240  Mmux__COND_1_inst_mux_f8_9 (_n0281<9>)
     LUT3:I2->O           32   0.720   0.000  Mmux__n0033_Result<9>1 (_n0033<9>)
     FDCE_1:D                  0.502          ram_data_7_9
    ----------------------------------------
    Total                      5.342ns (4.637ns logic, 0.705ns route)
                                       (86.8% logic, 13.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clkin'
Delay:               10.693ns (Levels of Logic = 47)
  Source:            my_dds4_DDS60_counterclk_cout_0 (FF)
  Destination:       my_dds4_DDS60_counterclk_cout_25 (FF)
  Source Clock:      clkin rising
  Destination Clock: clkin rising

  Data Path: my_dds4_DDS60_counterclk_cout_0 to my_dds4_DDS60_counterclk_cout_25
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            3   0.619   0.577  my_dds4_DDS60_counterclk_cout_0 (my_dds4_DDS60_counterclk_cout_0)
     LUT4_L:I0->LO         1   0.720   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_lut4_61 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_lut4_6)
     MUXCY:S->O            1   0.629   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_35 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_35)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_36 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_36)
     MUXCY:CI->O           1   0.091   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_37 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_37)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_38 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_38)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_39 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_39)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_40 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_40)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_41 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_41)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_42 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_42)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_43 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_43)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_44 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_44)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_45 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_45)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_46 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_46)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_47 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_47)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_48 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_48)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_49 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_49)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_50 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_50)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_51 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_51)
     MUXCY:CI->O          28   0.331   1.317  my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_52 (my_dds4_DDS60_counterclk_Mcompar__n0002_inst_cy_52)
     LUT1_L:I0->LO         1   0.720   0.000  my_dds4_DDS60_counterclk__n0002_rt (my_dds4_DDS60_counterclk__n0002_rt)
     MUXCY:S->O            1   0.629   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_55 (my_dds4_DDS60_counterclk_cout_inst_cy_55)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_56 (my_dds4_DDS60_counterclk_cout_inst_cy_56)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_57 (my_dds4_DDS60_counterclk_cout_inst_cy_57)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_58 (my_dds4_DDS60_counterclk_cout_inst_cy_58)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_59 (my_dds4_DDS60_counterclk_cout_inst_cy_59)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_60 (my_dds4_DDS60_counterclk_cout_inst_cy_60)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_61 (my_dds4_DDS60_counterclk_cout_inst_cy_61)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_62 (my_dds4_DDS60_counterclk_cout_inst_cy_62)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_63 (my_dds4_DDS60_counterclk_cout_inst_cy_63)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_64 (my_dds4_DDS60_counterclk_cout_inst_cy_64)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_65 (my_dds4_DDS60_counterclk_cout_inst_cy_65)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_66 (my_dds4_DDS60_counterclk_cout_inst_cy_66)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_67 (my_dds4_DDS60_counterclk_cout_inst_cy_67)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_68 (my_dds4_DDS60_counterclk_cout_inst_cy_68)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_69 (my_dds4_DDS60_counterclk_cout_inst_cy_69)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_70 (my_dds4_DDS60_counterclk_cout_inst_cy_70)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_71 (my_dds4_DDS60_counterclk_cout_inst_cy_71)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_72 (my_dds4_DDS60_counterclk_cout_inst_cy_72)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_73 (my_dds4_DDS60_counterclk_cout_inst_cy_73)
     MUXCY:CI->O           1   0.091   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_74 (my_dds4_DDS60_counterclk_cout_inst_cy_74)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_75 (my_dds4_DDS60_counterclk_cout_inst_cy_75)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_76 (my_dds4_DDS60_counterclk_cout_inst_cy_76)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_77 (my_dds4_DDS60_counterclk_cout_inst_cy_77)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_78 (my_dds4_DDS60_counterclk_cout_inst_cy_78)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_79 (my_dds4_DDS60_counterclk_cout_inst_cy_79)
     MUXCY:CI->O           0   0.090   0.000  my_dds4_DDS60_counterclk_cout_inst_cy_80 (my_dds4_DDS60_counterclk_cout_inst_cy_80)
     XORCY:CI->O           1   0.939   0.000  my_dds4_DDS60_counterclk_cout_inst_sum_41 (my_dds4_DDS60_counterclk_cout_inst_sum_41)
     FDCPE:D                   0.502          my_dds4_DDS60_counterclk_cout_25
    ----------------------------------------
    Total                     10.693ns (8.799ns logic, 1.894ns route)
                                       (82.3% logic, 17.7% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'my_dds4_DDS60_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            my_dds4_DDS60_PHA_ACC_t1_0 (FF)
  Destination:       my_dds4_DDS60_PHA_ACC_t1_15 (FF)
  Source Clock:      my_dds4_DDS60_counterclk_outclktemp:Q rising
  Destination Clock: my_dds4_DDS60_counterclk_outclktemp:Q rising

  Data Path: my_dds4_DDS60_PHA_ACC_t1_0 to my_dds4_DDS60_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  my_dds4_DDS60_PHA_ACC_t1_0 (my_dds4_DDS60_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_0 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_1 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_2 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_3 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_4 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_5 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_6 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_7 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_8 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_9 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_10 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_11 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_12 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_13 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_14 (my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  my_dds4_DDS60_PHA_ACC_t1_Madd__n0000_inst_sum_15 (my_dds4_DDS60_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          my_dds4_DDS60_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'my_dds4_DDS50_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            my_dds4_DDS50_PHA_ACC_t1_0 (FF)
  Destination:       my_dds4_DDS50_PHA_ACC_t1_15 (FF)
  Source Clock:      my_dds4_DDS50_counterclk_outclktemp:Q rising
  Destination Clock: my_dds4_DDS50_counterclk_outclktemp:Q rising

  Data Path: my_dds4_DDS50_PHA_ACC_t1_0 to my_dds4_DDS50_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  my_dds4_DDS50_PHA_ACC_t1_0 (my_dds4_DDS50_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_0 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_1 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_2 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_3 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_4 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_5 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_6 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_7 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_8 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_9 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_10 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_11 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_12 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_13 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_14 (my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  my_dds4_DDS50_PHA_ACC_t1_Madd__n0000_inst_sum_15 (my_dds4_DDS50_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          my_dds4_DDS50_PHA_ACC_t1_15
    ----------------------------------------