top.syr

Verilog编程

    Found 1-bit register for signal <SCLR1>.
    Found 1-bit register for signal <SCLR2>.
    Found 1-bit register for signal <SCLR3>.
    Found 1-bit register for signal <SCLR4>.
    Found 1-bit register for signal <SCLR5>.
    Found 1-bit register for signal <SCLR6>.
    Found 1-bit register for signal <WE1>.
    Found 1-bit register for signal <WE2>.
    Found 1-bit register for signal <WE3>.
    Found 1-bit register for signal <WE4>.
    Found 1-bit register for signal <WE5>.
    Found 1-bit register for signal <WE6>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <dds4> synthesized.


Synthesizing Unit <my_dcm1>.
    Related source file is my_dcm1.v.
Unit <my_dcm1> synthesized.


Synthesizing Unit <top>.
    Related source file is top.v.
    Found 16-bit 32-to-1 multiplexer for signal <$COND_1>.
    Found 16-bit register for signal <CONTROL>.
    Found 16-bit register for signal <DATA_FRE1>.
    Found 16-bit register for signal <DATA_FRE2>.
    Found 16-bit register for signal <DATA_FRE3>.
    Found 16-bit register for signal <DATA_FRE4>.
    Found 16-bit register for signal <DATA_FRE5>.
    Found 16-bit register for signal <DATA_FRE6>.
    Found 16-bit register for signal <DATA_PHA1>.
    Found 16-bit register for signal <DATA_PHA2>.
    Found 16-bit register for signal <DATA_PHA3>.
    Found 16-bit register for signal <DATA_PHA4>.
    Found 16-bit register for signal <DATA_PHA5>.
    Found 16-bit register for signal <DATA_PHA6>.
    Found 16-bit register for signal <PHA_ACC1>.
    Found 16-bit register for signal <PHA_ACC2>.
    Found 16-bit register for signal <PHA_ACC3>.
    Found 16-bit register for signal <PHA_ACC4>.
    Found 16-bit register for signal <PHA_ACC5>.
    Found 16-bit register for signal <PHA_ACC6>.
    Found 512-bit register for signal <ram_data>.
    Found 16-bit register for signal <trig>.
    Found 16 1-bit 2-to-1 multiplexers.
INFO:Xst:738 - HDL ADVISOR - 512 flip-flops were inferred for signal <ram_data>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
    Summary:
	inferred 688 D-type flip-flop(s).
	inferred  32 Multiplexer(s).
Unit <top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 100
  1-bit register                   : 18
  16-bit register                  : 76
  2-bit register                   : 6
# Counters                         : 6
  26-bit up counter                : 6
# Accumulators                     : 12
  16-bit up accumulator            : 12
# Multiplexers                     : 2
  2-to-1 multiplexer               : 1
  16-bit 32-to-1 multiplexer       : 1
# Adders/Subtractors               : 24
  16-bit adder                     : 12
  1-bit adder                      : 6
  3-bit subtractor                 : 6
# Multipliers                      : 6
  11x3-bit multiplier              : 6
# Comparators                      : 12
  28-bit comparator greatequal     : 6
  32-bit comparator greatequal     : 6

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "rom1.ngo" is up to date.
Loading core <rom1> for timing and area information for instance <rom>.
WARNING:Xst:1291 - FF/Latch <acc_0> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_1> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_2> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_3> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_4> is unconnected in block <DDS1>.
WARNING:Xst:1710 - FF/Latch  <flag_0> (without init value) is constant in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <CONTROL_0> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <CONTROL_1> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <CONTROL_2> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <CONTROL_3> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <CONTROL_0> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <CONTROL_1> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <CONTROL_2> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <CONTROL_3> is unconnected in block <top>.

Optimizing unit <top> ...

Optimizing unit <DDS1> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 32.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 97

Macro Statistics :
# Registers                        : 247
#      1-bit register              : 162
#      16-bit register             : 79
#      2-bit register              : 6
# Counters                         : 6
#      26-bit up counter           : 6
# Multiplexers                     : 2
#      16-bit 32-to-1 multiplexer  : 1
#      2-to-1 multiplexer          : 1
# Adders/Subtractors               : 24
#      16-bit adder                : 24
# Multipliers                      : 6
#      11x3-bit multiplier         : 6
# Comparators                      : 12
#      28-bit comparator greatequal: 6
#      32-bit comparator greatequal: 6

Cell Usage :
# BELS                             : 2599
#      BUF                         : 3
#      GND                         : 7
#      LUT1                        : 103
#      LUT1_L                      : 78
#      LUT2                        : 292
#      LUT2_L                      : 258
#      LUT3                        : 278
#      LUT3_L                      : 6
#      LUT4                        : 67
#      LUT4_L                      : 30
#      MUXCY                       : 744
#      MUXF5                       : 128
#      MUXF6                       : 64
#      MUXF7                       : 32
#      MUXF8                       : 16
#      VCC                         : 1
#      XORCY                       : 492
# FlipFlops/Latches                : 1554
#      FDC                         : 291
#      FDCE                        : 588
#      FDCE_1                      : 487
#      FDCPE                       : 156
#      FDP                         : 7
#      FDPE_1                      : 25
# RAMS                             : 6
#      RAMB16_S18                  : 6
# Clock Buffers                    : 4
#      BUFG                        : 3
#      BUFGP                       : 1
# IO Buffers                       : 96
#      IBUF                        : 23
#      IBUFG                       : 1
#      OBUF                        : 72
# DCMs                             : 1
#      DCM                         : 1
# MULTs                            : 6
#      MULT18X18                   : 6
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                    1222  out of   3584    34%  
 Number of Slice Flip Flops:          1554  out of   7168    21%  
 Number of 4 input LUTs:              1112  out of   7168    15%  
 Number of bonded IOBs:                 96  out of    141    68%