top.syr

Verilog编程

Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:Xst:878 - rom1.v line 98: Unrecognized directive. Ignoring.
Compiling source file "my_dcm1.v"
Module <my_dcm1> compiled
Compiling source file "counter.v"
Module <counter> compiled
Compiling source file "rom1.v"
Module <rom1> compiled
Compiling source file "DDS1.v"
Module <DDS1> compiled
Compiling source file "dds4.v"
Module <dds4> compiled
Compiling source file "top.v"
Module <top> compiled
No errors in compilation
Analysis of file <top.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
Analyzing top module <top>.
Module <top> is correct for synthesis.
 
Analyzing module <my_dcm1>.
Module <my_dcm1> is correct for synthesis.
 
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKDV_DIVIDE =  2" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKFX_DIVIDE =  2" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKFX_MULTIPLY =  2" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKIN_PERIOD =  20" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <my_dcm1>.
Analyzing module <DCM>.
Analyzing module <IBUFG>.
Analyzing module <BUFG>.
Analyzing module <dds4>.
Module <dds4> is correct for synthesis.
 
Analyzing module <DDS1>.
Module <DDS1> is correct for synthesis.
 
Analyzing module <counter>.
WARNING:Xst:854 - counter.v line 10: Ignored initial statement.
Module <counter> is correct for synthesis.
 
Analyzing module <rom1>.
WARNING:Xst:37 - Unknown property "fpga_dont_touch".

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is counter.v.
    Found 28-bit comparator greatequal for signal <$n0002> created at line 27.
    Found 32-bit comparator greatequal for signal <$n0004> created at line 32.
    Found 26-bit up counter for signal <cout>.
    Found 1-bit register for signal <outclktemp>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <counter> synthesized.


Synthesizing Unit <DDS1>.
    Related source file is DDS1.v.
WARNING:Xst:646 - Signal <acc<4:0>> is assigned but never used.
WARNING:Xst:643 - The result of a 11x3-bit multiplication found at line 107 is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 16-bit adder for signal <$n0003> created at line 76.
    Found 1-bit adder for signal <$n0005> created at line 107.
    Found 3-bit subtractor for signal <$n0007> created at line 107.
    Found 16-bit adder for signal <$n0008>.
    Found 11x3-bit multiplier for signal <$n0009> created at line 107.
    Found 16-bit register for signal <acc>.
    Found 16-bit up accumulator for signal <acc_t>.
    Found 16-bit register for signal <DATA_FRE_t>.
    Found 16-bit register for signal <DATA_PHA_t>.
    Found 2-bit register for signal <flag>.
    Found 16-bit register for signal <PHA_ACC_t>.
    Found 16-bit up accumulator for signal <PHA_ACC_t1>.
    Summary:
	inferred   2 Accumulator(s).
	inferred  66 D-type flip-flop(s).
	inferred   4 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <DDS1> synthesized.


Synthesizing Unit <dds4>.
    Related source file is dds4.v.
WARNING:Xst:647 - Input <CONTROL<3:0>> is never used.