shuzibiao.map.summary

来自「数字钟的verilog代码」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Thu Feb 21 19:53:50 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : shuzibiao
Top-level Entity Name : shuzibiao
Family : Stratix
Total logic elements : 151
Total pins : 26
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0