shuzibiao.hier_info

数字钟的verilog代码

|shuzibiao
bitout[0] <= LED:inst6.bitout[0]
bitout[1] <= LED:inst6.bitout[1]
bitout[2] <= LED:inst6.bitout[2]
bitout[3] <= LED:inst6.bitout[3]
clk3 => LED:inst6.clk3
clk1 => main:inst1.clk1
clk2 => main:inst1.clk2
clr => main:inst1.clr
Reset => main:inst1.Reset
paomiao => main:inst1.paomiao
LD1 => main:inst1.LD1
LD2 => main:inst1.LD2
LD3 => main:inst1.LD3
LD4 => main:inst1.LD4
data_in[0] => main:inst1.data_in[0]
data_in[1] => main:inst1.data_in[1]
data_in[2] => main:inst1.data_in[2]
data_in[3] => main:inst1.data_in[3]
segout[0] <= LED:inst6.segout[0]
segout[1] <= LED:inst6.segout[1]
segout[2] <= LED:inst6.segout[2]
segout[3] <= LED:inst6.segout[3]
segout[4] <= LED:inst6.segout[4]
segout[5] <= LED:inst6.segout[5]
segout[6] <= LED:inst6.segout[6]
segout[7] <= LED:inst6.segout[7]


|shuzibiao|LED:inst6
clk3 => segout[6]~reg0.CLK
clk3 => segout[5]~reg0.CLK
clk3 => segout[4]~reg0.CLK
clk3 => segout[3]~reg0.CLK
clk3 => segout[2]~reg0.CLK
clk3 => segout[1]~reg0.CLK
clk3 => segout[0]~reg0.CLK
clk3 => bitout[3]~reg0.CLK
clk3 => bitout[2]~reg0.CLK
clk3 => bitout[1]~reg0.CLK
clk3 => bitout[0]~reg0.CLK
clk3 => segout[7]~reg0.CLK
clk3 => state~4.IN1
segout[0] <= segout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
segout[1] <= segout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
segout[2] <= segout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
segout[3] <= segout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
segout[4] <= segout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
segout[5] <= segout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
segout[6] <= segout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
segout[7] <= segout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitout[0] <= bitout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitout[1] <= bitout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitout[2] <= bitout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitout[3] <= bitout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D1[0] => Selector7.IN0
D1[1] => Selector6.IN0
D1[2] => Selector5.IN0
D1[3] => Selector4.IN0
D1[4] => Selector3.IN0
D1[5] => Selector2.IN0
D1[6] => Selector1.IN0
D1[7] => Selector0.IN0
D2[0] => Selector7.IN1
D2[1] => Selector6.IN1
D2[2] => Selector5.IN1
D2[3] => Selector4.IN1
D2[4] => Selector3.IN1
D2[5] => Selector2.IN1
D2[6] => Selector1.IN1
D2[7] => Selector0.IN1
D3[0] => Selector7.IN2
D3[1] => Selector6.IN2
D3[2] => Selector5.IN2
D3[3] => Selector4.IN2
D3[4] => Selector3.IN2
D3[5] => Selector2.IN2
D3[6] => Selector1.IN2
D3[7] => Selector0.IN2
D4[0] => Selector7.IN3
D4[1] => Selector6.IN3
D4[2] => Selector5.IN3
D4[3] => Selector4.IN3
D4[4] => Selector3.IN3
D4[5] => Selector2.IN3
D4[6] => Selector1.IN3
D4[7] => Selector0.IN3


|shuzibiao|bianma:inst
D[0] => Decoder0.IN3
D[1] => Decoder0.IN2
D[2] => Decoder0.IN1
D[3] => Decoder0.IN0
out[0] <= <VCC>
out[1] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[7] <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|shuzibiao|main:inst1
clk1 => L1[2].CLK
clk1 => L1[1].CLK
clk1 => L1[0].CLK
clk1 => L2[3].CLK
clk1 => L2[2].CLK
clk1 => L2[1].CLK
clk1 => L2[0].CLK
clk1 => L3[3].CLK
clk1 => L3[2].CLK
clk1 => L3[1].CLK
clk1 => L3[0].CLK
clk1 => L4[3].CLK
clk1 => L4[2].CLK
clk1 => L4[1].CLK
clk1 => L4[0].CLK
clk1 => over1.CLK
clk1 => L1[3].CLK
clk2 => P1[2].CLK
clk2 => P1[1].CLK
clk2 => P1[0].CLK
clk2 => P2[3].CLK
clk2 => P2[2].CLK
clk2 => P2[1].CLK
clk2 => P2[0].CLK
clk2 => P3[3].CLK
clk2 => P3[2].CLK
clk2 => P3[1].CLK
clk2 => P3[0].CLK
clk2 => P4[3].CLK
clk2 => P4[2].CLK
clk2 => P4[1].CLK
clk2 => P4[0].CLK
clk2 => over2.CLK
clk2 => D1[3]~reg0.CLK
clk2 => D1[2]~reg0.CLK
clk2 => D1[1]~reg0.CLK
clk2 => D1[0]~reg0.CLK
clk2 => D2[3]~reg0.CLK
clk2 => D2[2]~reg0.CLK
clk2 => D2[1]~reg0.CLK
clk2 => D2[0]~reg0.CLK
clk2 => D3[3]~reg0.CLK
clk2 => D3[2]~reg0.CLK
clk2 => D3[1]~reg0.CLK
clk2 => D3[0]~reg0.CLK
clk2 => D4[3]~reg0.CLK
clk2 => D4[2]~reg0.CLK
clk2 => D4[1]~reg0.CLK
clk2 => D4[0]~reg0.CLK
clk2 => P1[3].CLK
clr => L1~0.OUTPUTSELECT
clr => L1~1.OUTPUTSELECT
clr => L1~2.OUTPUTSELECT
clr => L1~3.OUTPUTSELECT
clr => L2~0.OUTPUTSELECT
clr => L2~1.OUTPUTSELECT
clr => L2~2.OUTPUTSELECT
clr => L2~3.OUTPUTSELECT
clr => L3~0.OUTPUTSELECT
clr => L3~1.OUTPUTSELECT
clr => L3~2.OUTPUTSELECT
clr => L3~3.OUTPUTSELECT
clr => L4~0.OUTPUTSELECT
clr => L4~1.OUTPUTSELECT
clr => L4~2.OUTPUTSELECT
clr => L4~3.OUTPUTSELECT
clr => over1~0.OUTPUTSELECT
clr => always1~0.IN0
Reset => L1~8.OUTPUTSELECT
Reset => L1~9.OUTPUTSELECT
Reset => L1~10.OUTPUTSELECT
Reset => L1~11.OUTPUTSELECT
Reset => L4~12.OUTPUTSELECT
Reset => L4~13.OUTPUTSELECT
Reset => L4~14.OUTPUTSELECT
Reset => L4~15.OUTPUTSELECT
Reset => L3~16.OUTPUTSELECT
Reset => L3~17.OUTPUTSELECT
Reset => L3~18.OUTPUTSELECT
Reset => L3~19.OUTPUTSELECT
Reset => over1~3.OUTPUTSELECT
Reset => always0~2.IN1
Reset => always1~1.IN0
paomiao => always1~1.IN1
paomiao => D1~0.OUTPUTSELECT
paomiao => D1~1.OUTPUTSELECT
paomiao => D1~2.OUTPUTSELECT
paomiao => D1~3.OUTPUTSELECT
paomiao => D2~0.OUTPUTSELECT
paomiao => D2~1.OUTPUTSELECT
paomiao => D2~2.OUTPUTSELECT
paomiao => D2~3.OUTPUTSELECT
paomiao => D3~0.OUTPUTSELECT
paomiao => D3~1.OUTPUTSELECT
paomiao => D3~2.OUTPUTSELECT
paomiao => D3~3.OUTPUTSELECT
paomiao => D4~0.OUTPUTSELECT
paomiao => D4~1.OUTPUTSELECT
paomiao => D4~2.OUTPUTSELECT
paomiao => D4~3.OUTPUTSELECT
paomiao => always1~0.IN1
D1[0] <= D1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D1[1] <= D1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D1[2] <= D1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D1[3] <= D1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D2[0] <= D2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D2[1] <= D2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D2[2] <= D2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D2[3] <= D2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D3[0] <= D3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D3[1] <= D3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D3[2] <= D3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D3[3] <= D3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D4[0] <= D4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D4[1] <= D4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D4[2] <= D4[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D4[3] <= D4[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LD1 => always0~0.IN1
LD2 => always0~1.IN1
LD3 => L3~4.OUTPUTSELECT
LD3 => L3~5.OUTPUTSELECT
LD3 => L3~6.OUTPUTSELECT
LD3 => L3~7.OUTPUTSELECT
LD4 => L4~4.OUTPUTSELECT
LD4 => L4~5.OUTPUTSELECT
LD4 => L4~6.OUTPUTSELECT
LD4 => L4~7.OUTPUTSELECT
data_in[0] => LessThan0.IN8
data_in[0] => L1~7.DATAB
data_in[0] => LessThan1.IN8
data_in[0] => L2~7.DATAB
data_in[0] => L3~7.DATAB
data_in[0] => L4~7.DATAB
data_in[1] => LessThan0.IN7
data_in[1] => L1~6.DATAB
data_in[1] => LessThan1.IN7
data_in[1] => L2~6.DATAB
data_in[1] => L3~6.DATAB
data_in[1] => L4~6.DATAB
data_in[2] => LessThan0.IN6
data_in[2] => L1~5.DATAB
data_in[2] => LessThan1.IN6
data_in[2] => L2~5.DATAB
data_in[2] => L3~5.DATAB
data_in[2] => L4~5.DATAB
data_in[3] => LessThan0.IN5
data_in[3] => L1~4.DATAB
data_in[3] => LessThan1.IN5
data_in[3] => L2~4.DATAB
data_in[3] => L3~4.DATAB
data_in[3] => L4~4.DATAB


|shuzibiao|bianma:inst3
D[0] => Decoder0.IN3
D[1] => Decoder0.IN2
D[2] => Decoder0.IN1
D[3] => Decoder0.IN0
out[0] <= <VCC>
out[1] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[7] <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|shuzibiao|bianma:inst4
D[0] => Decoder0.IN3
D[1] => Decoder0.IN2
D[2] => Decoder0.IN1
D[3] => Decoder0.IN0
out[0] <= <VCC>
out[1] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[7] <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|shuzibiao|bianma:inst5
D[0] => Decoder0.IN3
D[1] => Decoder0.IN2
D[2] => Decoder0.IN1
D[3] => Decoder0.IN0
out[0] <= <VCC>
out[1] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[7] <= out~0.DB_MAX_OUTPUT_PORT_TYPE