shuzibiao.tan.summary

数字钟的verilog代码

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.810 ns
From           : data_in[0]
To             : main:inst1|L1[3]
From Clock     : --
To Clock       : clk1
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.127 ns
From           : LED:inst6|bitout[0]
To             : bitout[0]
From Clock     : clk3
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.192 ns
From           : LD4
To             : main:inst1|L4[1]
From Clock     : --
To Clock       : clk1
Failed Paths   : 0

Type           : Clock Setup: 'clk2'
Slack          : N/A
Required Time  : None
Actual Time    : 294.55 MHz ( period = 3.395 ns )
From           : main:inst1|P4[0]
To             : main:inst1|P3[3]
From Clock     : clk2
To Clock       : clk2
Failed Paths   : 0

Type           : Clock Setup: 'clk1'
Slack          : N/A
Required Time  : None
Actual Time    : 299.40 MHz ( period = 3.340 ns )
From           : main:inst1|L4[1]
To             : main:inst1|L4[2]
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 0

Type           : Clock Setup: 'clk3'
Slack          : N/A
Required Time  : None
Actual Time    : 373.97 MHz ( period = 2.674 ns )
From           : LED:inst6|state.S3
To             : LED:inst6|segout[4]
From Clock     : clk3
To Clock       : clk3
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------