main.v

数字钟的verilog代码

module main(clk1,clk2,clr,Reset,paomiao,D1,D2,D3,D4,LD1,LD2,LD3,LD4,data_in);
input clk1,clk2,clr,Reset,paomiao,LD1,LD2,LD3,LD4;
input[3:0]data_in;
output [3:0]D1,D2,D3,D4;
reg [3:0]D1,D2,D3,D4;
reg [3:0]L1,L2,L3,L4,P1,P2,P3,P4;
reg a,over1,over2;


always@(posedge clk1)
  begin
  if(clr)      //qing ling,
     begin
     {L1,L2,L3,L4}<=16'b0;
     over1<=0;
     end 
  if(Reset)//shi zhong tiao zheng,
      if((LD1==1)&&(data_in<=2)) L1<=data_in;
      if((LD2==1)&&(data_in<=4)) L2<=data_in;
      if(LD3==1) L3<=data_in;
      if(LD4==1) L4<=data_in;
      else;
  if((!Reset)&&(over1==1))
    begin
      if((L1==2)&&(L2==3))
               begin {L1,L2}<=8'b0;end
      else if (L2==9)
               begin  L1<=L1+1;L2<=0;end
      else begin  L2<=L2+1;end
    end
   if(!Reset)    //fei zhi wei,
     begin 
        if(L4==9)
          begin 
            L4<=0;
           if(L3==5)
            begin  L3<=0;over1<=1;end
           else  L3<=L3+1;
          end
        else begin
             L4<=L4+1;over1<=0;
             end
     end
  end

always@(posedge clk2)//pao miao
 begin
   if(clr||(!paomiao))      //qing ling,
     begin
     {P1,P2,P3,P4}<=16'b0;
     over2<=0;
     end 
   if((!Reset)&&(paomiao==1)&&(over2==1))
    begin
      if(P2==9)
          begin 
            P2<=0;
           if(P1==9)
            begin  P1<=0;end
           else  P1<=P1+1;
          end
      else begin P2<=P2+1;end
    end
   if((!Reset)&&(paomiao==1))
     begin 
        if(P4==9)
          begin 
            P4<=0;
           if(P3==9)
            begin  P3<=0;over2<=1;end
           else  P3<=P3+1;
          end
        else begin
             P4<=P4+1;over2<=0;
             end
     end
  end

always@(posedge clk2)
 begin   
   if(paomiao)
        begin  D1<=P1;D2<=P2;D3<=P3;D4<=P4;end
   else begin  D1<=L1;D2<=L2;D3<=L3;D4<=L4;end
 end

endmodule