m2_0610.map.rpt

在ALTERA公司的EPM570上实现的电机脉冲算法

; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EPM240T100C5       ;                    ;
; Top-level entity name                                                          ; ZHUHAI             ; M2_0610            ;
; Family name                                                                    ; MAX II             ; Stratix            ;
; Type of Retiming Performed During Resynthesis                                  ; Full               ;                    ;
; Resynthesis Optimization Effort                                                ; Normal             ;                    ;
; Physical Synthesis Level for Resynthesis                                       ; Normal             ;                    ;
; Use Generated Physical Constraints File                                        ; On                 ;                    ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- MAX II                                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                                       ; On                 ; On                 ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; ZHUHAI.bdf                       ; yes             ; User Block Diagram/Schematic File  ; E:/珠海/cpld/ZHUHAI.bdf                                              ;
; PULSE_GEN.bdf                    ; yes             ; User Block Diagram/Schematic File  ; E:/珠海/cpld/PULSE_GEN.bdf                                           ;
; WATCH_DOG.bdf                    ; yes             ; User Block Diagram/Schematic File  ; E:/珠海/cpld/WATCH_DOG.bdf                                           ;
; Filter.bdf                       ; yes             ; User Block Diagram/Schematic File  ; E:/珠海/cpld/Filter.bdf                                              ;
; QEP_CNT.bdf                      ; yes             ; User Block Diagram/Schematic File  ; E:/珠海/cpld/QEP_CNT.bdf                                             ;
; LPM_OR3.vhd                      ; yes             ; Other                              ; E:/珠海/cpld/LPM_OR3.vhd                                             ;
; LPM_OR.tdf                       ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/LPM_OR.tdf              ;
; aglobal71.inc                    ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/aglobal71.inc           ;
; LPM_AND2.vhd                     ; yes             ; Other                              ; E:/珠海/cpld/LPM_AND2.vhd                                            ;
; LPM_AND.tdf                      ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/LPM_AND.tdf             ;
; LPM_FD1.vhd                      ; yes             ; Other                              ; E:/珠海/cpld/LPM_FD1.vhd                                             ;
; lpm_ff.tdf                       ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf              ;
; lpm_constant.inc                 ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/lpm_constant.inc        ;
; COUNTER16.vhd                    ; yes             ; Other                              ; E:/珠海/cpld/COUNTER16.vhd                                           ;
; lpm_counter.tdf                  ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Megafunction                       ; d:/altera/71/quartus/libraries/megafunctions/dffeea.inc              ;