register1.v

用verilog写的电梯控制器

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    08:45:51 01/08/07
// Design Name:    
// Module Name:    register1
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module register1 (register_out,register_in,clk,reset,load_enable);
parameter width=8;

output[width-1:0] register_out;
input[width-1:0] register_in;
input clk;
input reset;
input load_enable;
reg [width-1:0] register_out;

always @( posedge clk or negedge reset )
begin
    if(!reset)
    register_out<=1;
    else
    begin 
     if(load_enable)
       register_out<=register_in;
      else
       register_out<=register_out;
    end     
end
endmodule