jtag.fit.qmsg

Altera公司调试CPLD/FPGA用的USBblaster的制作文档

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.620 ns register pin " "Info: Estimated most critical path is register to pin delay of 4.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jtag_logic:inst6\|B_TCK 1 REG LAB_X5_Y1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y1; Fanout = 2; REG Node = 'jtag_logic:inst6\|B_TCK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { jtag_logic:inst6|B_TCK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.298 ns) + CELL(2.322 ns) 4.620 ns TCK1 2 PIN PIN_2 0 " "Info: 2: + IC(2.298 ns) + CELL(2.322 ns) = 4.620 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'TCK1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.620 ns" { jtag_logic:inst6|B_TCK TCK1 } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -824 1080 1256 -808 "TCK1" "" } { -856 952 1016 -840 "TCK1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 50.26 % ) " "Info: Total cell delay = 2.322 ns ( 50.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.298 ns ( 49.74 % ) " "Info: Total interconnect delay = 2.298 ns ( 49.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.620 ns" { jtag_logic:inst6|B_TCK TCK1 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "7 7 " "Info: Average interconnect usage is 7% of the available device resources. Peak interconnect usage is 7%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y5 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "jtag_logic:inst6\|D\[0\]~en " "Info: Following pins have the same output enable: jtag_logic:inst6\|D\[0\]~en" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FD\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin FD\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "FD\[6\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FD\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin FD\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "FD\[4\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FD\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin FD\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "FD\[2\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FD\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin FD\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "FD\[0\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FD\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin FD\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "FD\[7\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FD\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin FD\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "FD\[5\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FD\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin FD\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "FD\[3\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FD\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin FD\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "FD\[1\]" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "154 " "Info: Allocated 154 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 13 16:24:32 2007 " "Info: Processing ended: Wed Jun 13 16:24:32 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/JTAG 2006.06.13/1/JTAG.fit.smsg " "Info: Generated suppressed messages file G:/JTAG 2006.06.13/1/JTAG.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}