jtag.map.qmsg

Altera公司调试CPLD/FPGA用的USBblaster的制作文档

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 13 16:24:26 2007 " "Info: Processing started: Wed Jun 13 16:24:26 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off JTAG -c JTAG " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JTAG -c JTAG" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JTAG.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file JTAG.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG " "Info: Found entity 1: JTAG" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_logic.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jtag_logic.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jtag_logic-spec " "Info: Found design unit 1: jtag_logic-spec" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 42 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 jtag_logic " "Info: Found entity 1: jtag_logic" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 22 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "JTAG " "Info: Elaborating entity \"JTAG\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_logic jtag_logic:inst6 " "Info: Elaborating entity \"jtag_logic\" for hierarchy \"jtag_logic:inst6\"" {  } { { "JTAG.bdf" "inst6" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -872 816 952 -680 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "jtag_logic:inst6\|D\[1\]~en jtag_logic:inst6\|D\[0\]~en " "Info: Duplicate register \"jtag_logic:inst6\|D\[1\]~en\" merged to single register \"jtag_logic:inst6\|D\[0\]~en\"" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jtag_logic:inst6\|D\[2\]~en jtag_logic:inst6\|D\[0\]~en " "Info: Duplicate register \"jtag_logic:inst6\|D\[2\]~en\" merged to single register \"jtag_logic:inst6\|D\[0\]~en\"" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jtag_logic:inst6\|D\[3\]~en jtag_logic:inst6\|D\[0\]~en " "Info: Duplicate register \"jtag_logic:inst6\|D\[3\]~en\" merged to single register \"jtag_logic:inst6\|D\[0\]~en\"" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jtag_logic:inst6\|D\[4\]~en jtag_logic:inst6\|D\[0\]~en " "Info: Duplicate register \"jtag_logic:inst6\|D\[4\]~en\" merged to single register \"jtag_logic:inst6\|D\[0\]~en\"" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jtag_logic:inst6\|D\[5\]~en jtag_logic:inst6\|D\[0\]~en " "Info: Duplicate register \"jtag_logic:inst6\|D\[5\]~en\" merged to single register \"jtag_logic:inst6\|D\[0\]~en\"" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jtag_logic:inst6\|D\[6\]~en jtag_logic:inst6\|D\[0\]~en " "Info: Duplicate register \"jtag_logic:inst6\|D\[6\]~en\" merged to single register \"jtag_logic:inst6\|D\[0\]~en\"" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jtag_logic:inst6\|D\[7\]~en jtag_logic:inst6\|D\[0\]~en " "Info: Duplicate register \"jtag_logic:inst6\|D\[7\]~en\" merged to single register \"jtag_logic:inst6\|D\[0\]~en\"" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "87 " "Info: Implemented 87 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "70 " "Info: Implemented 70 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Allocated 139 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 13 16:24:30 2007 " "Info: Processing ended: Wed Jun 13 16:24:30 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}