jtag.tan.qmsg

Altera公司调试CPLD/FPGA用的USBblaster的制作文档

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK12MHz TCK1 jtag_logic:inst6\|B_TCK 9.016 ns register " "Info: tco from clock \"CLK12MHz\" to destination pin \"TCK1\" through register \"jtag_logic:inst6\|B_TCK\" is 9.016 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHz source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"CLK12MHz\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK12MHz 1 CLK PIN_12 38 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 38; CLK Node = 'CLK12MHz'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK12MHz } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -840 528 696 -824 "CLK12MHz" "" } { -856 752 817 -840 "CLK12MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns jtag_logic:inst6\|B_TCK 2 REG LC_X5_Y1_N8 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y1_N8; Fanout = 2; REG Node = 'jtag_logic:inst6\|B_TCK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK12MHz jtag_logic:inst6|B_TCK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|B_TCK } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|B_TCK } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.292 ns + Longest register pin " "Info: + Longest register to pin delay is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jtag_logic:inst6\|B_TCK 1 REG LC_X5_Y1_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N8; Fanout = 2; REG Node = 'jtag_logic:inst6\|B_TCK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { jtag_logic:inst6|B_TCK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.970 ns) + CELL(2.322 ns) 5.292 ns TCK1 2 PIN PIN_2 0 " "Info: 2: + IC(2.970 ns) + CELL(2.322 ns) = 5.292 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'TCK1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { jtag_logic:inst6|B_TCK TCK1 } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -824 1080 1256 -808 "TCK1" "" } { -856 952 1016 -840 "TCK1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 43.88 % ) " "Info: Total cell delay = 2.322 ns ( 43.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.970 ns ( 56.12 % ) " "Info: Total interconnect delay = 2.970 ns ( 56.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { jtag_logic:inst6|B_TCK TCK1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { jtag_logic:inst6|B_TCK TCK1 } { 0.000ns 2.970ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|B_TCK } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|B_TCK } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { jtag_logic:inst6|B_TCK TCK1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { jtag_logic:inst6|B_TCK TCK1 } { 0.000ns 2.970ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "jtag_logic:inst6\|ioshifter\[4\] FD\[4\] CLK12MHz -1.182 ns register " "Info: th for register \"jtag_logic:inst6\|ioshifter\[4\]\" (data pin = \"FD\[4\]\", clock pin = \"CLK12MHz\") is -1.182 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHz destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"CLK12MHz\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK12MHz 1 CLK PIN_12 38 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 38; CLK Node = 'CLK12MHz'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK12MHz } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -840 528 696 -824 "CLK12MHz" "" } { -856 752 817 -840 "CLK12MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns jtag_logic:inst6\|ioshifter\[4\] 2 REG LC_X5_Y2_N5 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N5; Fanout = 4; REG Node = 'jtag_logic:inst6\|ioshifter\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK12MHz jtag_logic:inst6|ioshifter[4] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|ioshifter[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|ioshifter[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.751 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FD\[4\] 1 PIN PIN_71 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'FD\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { FD[4] } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns FD~3 2 COMB IOC_X8_Y4_N3 1 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X8_Y4_N3; Fanout = 1; COMB Node = 'FD~3'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { FD[4] FD~3 } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -760 528 704 -744 "FD\[7..0\]" "" } { -728 952 1016 -712 "FD\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.558 ns) + CELL(1.061 ns) 4.751 ns jtag_logic:inst6\|ioshifter\[4\] 3 REG LC_X5_Y2_N5 4 " "Info: 3: + IC(2.558 ns) + CELL(1.061 ns) = 4.751 ns; Loc. = LC_X5_Y2_N5; Fanout = 4; REG Node = 'jtag_logic:inst6\|ioshifter\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.619 ns" { FD~3 jtag_logic:inst6|ioshifter[4] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 46.16 % ) " "Info: Total cell delay = 2.193 ns ( 46.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.558 ns ( 53.84 % ) " "Info: Total interconnect delay = 2.558 ns ( 53.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { FD[4] FD~3 jtag_logic:inst6|ioshifter[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.751 ns" { FD[4] FD~3 jtag_logic:inst6|ioshifter[4] } { 0.000ns 0.000ns 2.558ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|ioshifter[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|ioshifter[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { FD[4] FD~3 jtag_logic:inst6|ioshifter[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.751 ns" { FD[4] FD~3 jtag_logic:inst6|ioshifter[4] } { 0.000ns 0.000ns 2.558ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "99 " "Info: Allocated 99 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 13 16:24:41 2007 " "Info: Processing ended: Wed Jun 13 16:24:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}