jtag.tan.qmsg

Altera公司调试CPLD/FPGA用的USBblaster的制作文档

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK12MHz " "Info: Assuming node \"CLK12MHz\" is an undefined clock" {  } { { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -840 528 696 -824 "CLK12MHz" "" } { -856 752 817 -840 "CLK12MHz" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK12MHz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK12MHz register jtag_logic:inst6\|state\[3\] register jtag_logic:inst6\|state\[0\] 138.54 MHz 7.218 ns Internal " "Info: Clock \"CLK12MHz\" has Internal fmax of 138.54 MHz between source register \"jtag_logic:inst6\|state\[3\]\" and destination register \"jtag_logic:inst6\|state\[0\]\" (period= 7.218 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.509 ns + Longest register register " "Info: + Longest register to register delay is 6.509 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jtag_logic:inst6\|state\[3\] 1 REG LC_X5_Y1_N1 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N1; Fanout = 20; REG Node = 'jtag_logic:inst6\|state\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { jtag_logic:inst6|state[3] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.740 ns) 3.040 ns jtag_logic:inst6\|Mux3~628 2 COMB LC_X6_Y2_N2 1 " "Info: 2: + IC(2.300 ns) + CELL(0.740 ns) = 3.040 ns; Loc. = LC_X6_Y2_N2; Fanout = 1; COMB Node = 'jtag_logic:inst6\|Mux3~628'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.040 ns" { jtag_logic:inst6|state[3] jtag_logic:inst6|Mux3~628 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.200 ns) 3.959 ns jtag_logic:inst6\|Mux3~629 3 COMB LC_X6_Y2_N0 1 " "Info: 3: + IC(0.719 ns) + CELL(0.200 ns) = 3.959 ns; Loc. = LC_X6_Y2_N0; Fanout = 1; COMB Node = 'jtag_logic:inst6\|Mux3~629'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.919 ns" { jtag_logic:inst6|Mux3~628 jtag_logic:inst6|Mux3~629 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.746 ns) + CELL(0.804 ns) 6.509 ns jtag_logic:inst6\|state\[0\] 4 REG LC_X6_Y1_N8 19 " "Info: 4: + IC(1.746 ns) + CELL(0.804 ns) = 6.509 ns; Loc. = LC_X6_Y1_N8; Fanout = 19; REG Node = 'jtag_logic:inst6\|state\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.550 ns" { jtag_logic:inst6|Mux3~629 jtag_logic:inst6|state[0] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.744 ns ( 26.79 % ) " "Info: Total cell delay = 1.744 ns ( 26.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.765 ns ( 73.21 % ) " "Info: Total interconnect delay = 4.765 ns ( 73.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.509 ns" { jtag_logic:inst6|state[3] jtag_logic:inst6|Mux3~628 jtag_logic:inst6|Mux3~629 jtag_logic:inst6|state[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.509 ns" { jtag_logic:inst6|state[3] jtag_logic:inst6|Mux3~628 jtag_logic:inst6|Mux3~629 jtag_logic:inst6|state[0] } { 0.000ns 2.300ns 0.719ns 1.746ns } { 0.000ns 0.740ns 0.200ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHz destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK12MHz\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK12MHz 1 CLK PIN_12 38 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 38; CLK Node = 'CLK12MHz'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK12MHz } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -840 528 696 -824 "CLK12MHz" "" } { -856 752 817 -840 "CLK12MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns jtag_logic:inst6\|state\[0\] 2 REG LC_X6_Y1_N8 19 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y1_N8; Fanout = 19; REG Node = 'jtag_logic:inst6\|state\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK12MHz jtag_logic:inst6|state[0] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|state[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|state[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHz source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"CLK12MHz\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK12MHz 1 CLK PIN_12 38 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 38; CLK Node = 'CLK12MHz'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK12MHz } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -840 528 696 -824 "CLK12MHz" "" } { -856 752 817 -840 "CLK12MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns jtag_logic:inst6\|state\[3\] 2 REG LC_X5_Y1_N1 20 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y1_N1; Fanout = 20; REG Node = 'jtag_logic:inst6\|state\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK12MHz jtag_logic:inst6|state[3] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|state[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|state[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|state[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|state[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|state[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|state[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.509 ns" { jtag_logic:inst6|state[3] jtag_logic:inst6|Mux3~628 jtag_logic:inst6|Mux3~629 jtag_logic:inst6|state[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.509 ns" { jtag_logic:inst6|state[3] jtag_logic:inst6|Mux3~628 jtag_logic:inst6|Mux3~629 jtag_logic:inst6|state[0] } { 0.000ns 2.300ns 0.719ns 1.746ns } { 0.000ns 0.740ns 0.200ns 0.804ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|state[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|state[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|state[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|state[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "jtag_logic:inst6\|state\[1\] nTXE CLK12MHz 3.378 ns register " "Info: tsu for register \"jtag_logic:inst6\|state\[1\]\" (data pin = \"nTXE\", clock pin = \"CLK12MHz\") is 3.378 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.393 ns + Longest pin register " "Info: + Longest pin to register delay is 6.393 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns nTXE 1 PIN PIN_54 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_54; Fanout = 2; PIN Node = 'nTXE'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { nTXE } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -792 528 696 -776 "nTXE" "" } { -824 752 816 -808 "nTXE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.450 ns) + CELL(0.914 ns) 4.496 ns jtag_logic:inst6\|Mux3~625 2 COMB LC_X6_Y1_N6 2 " "Info: 2: + IC(2.450 ns) + CELL(0.914 ns) = 4.496 ns; Loc. = LC_X6_Y1_N6; Fanout = 2; COMB Node = 'jtag_logic:inst6\|Mux3~625'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.364 ns" { nTXE jtag_logic:inst6|Mux3~625 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.714 ns) + CELL(1.183 ns) 6.393 ns jtag_logic:inst6\|state\[1\] 3 REG LC_X6_Y1_N4 22 " "Info: 3: + IC(0.714 ns) + CELL(1.183 ns) = 6.393 ns; Loc. = LC_X6_Y1_N4; Fanout = 22; REG Node = 'jtag_logic:inst6\|state\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.897 ns" { jtag_logic:inst6|Mux3~625 jtag_logic:inst6|state[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.229 ns ( 50.51 % ) " "Info: Total cell delay = 3.229 ns ( 50.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.164 ns ( 49.49 % ) " "Info: Total interconnect delay = 3.164 ns ( 49.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.393 ns" { nTXE jtag_logic:inst6|Mux3~625 jtag_logic:inst6|state[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.393 ns" { nTXE nTXE~combout jtag_logic:inst6|Mux3~625 jtag_logic:inst6|state[1] } { 0.000ns 0.000ns 2.450ns 0.714ns } { 0.000ns 1.132ns 0.914ns 1.183ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHz destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK12MHz\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK12MHz 1 CLK PIN_12 38 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 38; CLK Node = 'CLK12MHz'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK12MHz } "NODE_NAME" } } { "JTAG.bdf" "" { Schematic "G:/JTAG 2006.06.13/1/JTAG.bdf" { { -840 528 696 -824 "CLK12MHz" "" } { -856 752 817 -840 "CLK12MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns jtag_logic:inst6\|state\[1\] 2 REG LC_X6_Y1_N4 22 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y1_N4; Fanout = 22; REG Node = 'jtag_logic:inst6\|state\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK12MHz jtag_logic:inst6|state[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "G:/JTAG 2006.06.13/1/jtag_logic.vhd" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|state[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|state[1] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.393 ns" { nTXE jtag_logic:inst6|Mux3~625 jtag_logic:inst6|state[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.393 ns" { nTXE nTXE~combout jtag_logic:inst6|Mux3~625 jtag_logic:inst6|state[1] } { 0.000ns 0.000ns 2.450ns 0.714ns } { 0.000ns 1.132ns 0.914ns 1.183ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK12MHz jtag_logic:inst6|state[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK12MHz CLK12MHz~combout jtag_logic:inst6|state[1] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}