jtag.tan.summary

Altera公司调试CPLD/FPGA用的USBblaster的制作文档

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.378 ns
From           : nTXE
To             : jtag_logic:inst6|state[1]
From Clock     : --
To Clock       : CLK12MHz
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.016 ns
From           : jtag_logic:inst6|B_TCK
To             : TCK1
From Clock     : CLK12MHz
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.182 ns
From           : FD[4]
To             : jtag_logic:inst6|ioshifter[4]
From Clock     : --
To Clock       : CLK12MHz
Failed Paths   : 0

Type           : Clock Setup: 'CLK12MHz'
Slack          : N/A
Required Time  : None
Actual Time    : 138.54 MHz ( period = 7.218 ns )
From           : jtag_logic:inst6|state[3]
To             : jtag_logic:inst6|state[0]
From Clock     : CLK12MHz
To Clock       : CLK12MHz
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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