spi_communication.v

单片机SPI通信模块verilog hdl

/*spi和cpld之间的通信模块，
还要控制da转换模块*/

module spi_communication(	mosi0,	/*单片机控制spi输入*/
							ssel_w,	/*write module select*/
							ssel_c,	/*控制命令输入*/
							ssel_r, /*read module select*/
							clk0,	/*单片机时钟控制*/
							clk1,	/*cpld时钟控制*/
							wave_out,	/*da输入，读出波形数据*/
							am_control,	/*da幅度控制*/
							address_control,	/*地址指针控制*/
							data,	/*ram的输入输出数据端口*/
							read,	/*读控制*/
							write	/*写控制*/
							);	


output 			write,read;
output 	[7:0]   am_control,
				wave_out;
output 	[31:0]  address_control;
				
inout 	[7:0] 	data;	
wire    [7:0]	  data;

reg 			write,read;
reg [7:0] 		am_control,
							wave_out;
	
reg [31:0] 		address_control,
							frequ_control; /*频率控制即步进量控制*/
reg [7:0]			counter;
reg [2:0] 		one_byte;
reg [7:0]       data_buf;
reg [31:0]      addr_t;
wire[31:0]      addr;

input   mosi0,
		ssel_w,
		ssel_c,
		ssel_r,
		clk0,
		clk1;

always@(posedge clk0) 
begin
	counter<=0;		/*记数初始化*/
	one_byte<=0;
			if(ssel_w)		/*选择写入*/
					begin
			read<=1'b0;		
			data_buf[7:0]<={data_buf[6:0],mosi0};
			one_byte<=one_byte+3'b001;
			
			if(one_byte==0)	/*够一个字节了，写入ram*/
			write<=1'b1;
			else 
			write<=1'b0;
			end
						
			else if(ssel_c)		/*选择写入控制命令*/	
			begin
						
			counter<=counter+1;
			if(counter<=7)
			am_control[7:0]<={am_control[6:0],mosi0};	/*首先输入的是幅度控制*/
			else if(counter<=39)
			addr_t[31:0]<={addr_t[30:0],mosi0};	/*地址指针*/
			else if(counter<=71)
			frequ_control[31:0]<={frequ_control[30:0],mosi0};	/*频率控制字*/
			
			end
						
			else if(ssel_r)		
						begin		
						read<=1'b1;	/*初始化*/
						write<=1'b0;
						end
			
								
						
end

assign data= (ssel_w)? data_buf : 8'hzz;
assign addr = read? (addr_t+frequ_control) : 0; 

always@(posedge clk1)
begin
			if(read==1)	   
			begin
			wave_out<=data;		/*读出的波形数据*/
	        address_control <= addr;
						/*频率控制*/
			end
end

endmodule