ord41.vhd

在MAX+PLUS II环境下用VHDL编写的加法器

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ORD41 IS
	PORT(
		A1, B1,C1, D1: IN	STD_LOGIC;
		Z1 : OUT	STD_LOGIC);
END ORD41;
ARCHITECTURE a OF ORD41 IS
	COMPONENT ND2 
		PORT(
        A, B: IN	STD_LOGIC;
		C: OUT	STD_LOGIC);
END COMPONENT;
SIGNAL S1,S2:STD_LOGIC;
BEGIN
U1:ND2 PORT MAP(A1,B1,S1);
U2:ND2 PORT MAP(C1,D1,S2);
U3:ND2 PORT MAP(S1,S2,Z1);
END a;