nd2.vhd

在MAX+PLUS II环境下用VHDL编写的加法器

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ND2 IS
	PORT(
		A, B: IN	STD_LOGIC;
		C : OUT	STD_LOGIC);
END ND2;
ARCHITECTURE a OF ND2 IS
	BEGIN
C<=A NAND B;
	END a;