h_adder.vhd

在EDA的MAX+PLUS II开发环境下用VHDL编写的全加器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_ADDER IS
   PORT(A,B: IN STD_LOGIC;CO,SO: OUT STD_LOGIC);
END ENTITY H_ADDER;
architecture ART2 Of H_ADDER IS
   BEGIN
   SO<=(A OR B)AND(A NAND B);
   CO<=NOT(A NAND B);
END ARCHITECTURE ART2;