orm2.vhd

在EDA的MAX+PLUS II开发环境下用VHDL编写的全加器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY orm2 IS
   PORT(A,B: IN STD_LOGIC;C: OUT STD_LOGIC);
END ENTITY ORM2;
architecture ART1 Of ORM2 IS
   BEGIN
   C<= A OR B;
END ARCHITECTURE ART1;